BE833310A - Dispositif pour enregistrer des signaux binaires dans des elements selectionnes d'une memoire mos - Google Patents

Dispositif pour enregistrer des signaux binaires dans des elements selectionnes d'une memoire mos

Info

Publication number
BE833310A
BE833310A BE159949A BE159949A BE833310A BE 833310 A BE833310 A BE 833310A BE 159949 A BE159949 A BE 159949A BE 159949 A BE159949 A BE 159949A BE 833310 A BE833310 A BE 833310A
Authority
BE
Belgium
Prior art keywords
binary signals
selected elements
mos memory
recording binary
recording
Prior art date
Application number
BE159949A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE833310A publication Critical patent/BE833310A/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
BE159949A 1974-09-11 1975-09-11 Dispositif pour enregistrer des signaux binaires dans des elements selectionnes d'une memoire mos BE833310A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742443529 DE2443529B2 (de) 1974-09-11 1974-09-11 Verfahren und anordnung zum einschreiben von binaersignalen in ausgewaehlte speicherelemente eines mos-speichers

Publications (1)

Publication Number Publication Date
BE833310A true BE833310A (fr) 1976-03-11

Family

ID=5925478

Family Applications (1)

Application Number Title Priority Date Filing Date
BE159949A BE833310A (fr) 1974-09-11 1975-09-11 Dispositif pour enregistrer des signaux binaires dans des elements selectionnes d'une memoire mos

Country Status (8)

Country Link
US (1) US3992704A (fr)
BE (1) BE833310A (fr)
CH (1) CH586946A5 (fr)
DE (1) DE2443529B2 (fr)
FR (1) FR2331121A1 (fr)
GB (1) GB1522183A (fr)
IT (1) IT1042254B (fr)
NL (1) NL7510186A (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069475A (en) * 1976-04-15 1978-01-17 National Semiconductor Corporation MOS Dynamic random access memory having an improved sense and restore circuit
US4069474A (en) * 1976-04-15 1978-01-17 National Semiconductor Corporation MOS Dynamic random access memory having an improved sensing circuit
US4144590A (en) * 1976-12-29 1979-03-13 Texas Instruments Incorporated Intermediate output buffer circuit for semiconductor memory device
US4081701A (en) * 1976-06-01 1978-03-28 Texas Instruments Incorporated High speed sense amplifier for MOS random access memory
US4114055A (en) * 1977-05-12 1978-09-12 Rca Corporation Unbalanced sense circuit
US4107556A (en) * 1977-05-12 1978-08-15 Rca Corporation Sense circuit employing complementary field effect transistors
US4096401A (en) * 1977-05-12 1978-06-20 Rca Corporation Sense circuit for an MNOS array using a pair of CMOS inverters cross-coupled via CMOS gates which are responsive to the input sense signals
JPS5939833B2 (ja) * 1977-05-24 1984-09-26 日本電気株式会社 センス増幅器
US4170741A (en) * 1978-03-13 1979-10-09 Westinghouse Electric Corp. High speed CMOS sense circuit for semiconductor memories
DE2839073C2 (de) * 1978-09-07 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Dynamische Stromquelle für Halbleiterbausteine und ihre Verwendung
JPS58114391A (ja) * 1981-12-25 1983-07-07 Nec Corp センスアンプ回路
US5352937A (en) * 1992-11-16 1994-10-04 Rca Thomson Licensing Corporation Differential comparator circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675218A (en) * 1970-01-15 1972-07-04 Ibm Independent read-write monolithic memory array
US3838295A (en) * 1973-02-05 1974-09-24 Lockheed Electronics Co Ratioless mos sense amplifier
DE2309192C3 (de) * 1973-02-23 1975-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Regenerierschaltung nach Art eines getasteten Flipflops und Verfahren zum Betrieb einer solchen Regenerierschaltung
US3838404A (en) * 1973-05-17 1974-09-24 Teletype Corp Random access memory system and cell
US3940747A (en) * 1973-08-02 1976-02-24 Texas Instruments Incorporated High density, high speed random access read-write memory
US3863232A (en) * 1973-12-26 1975-01-28 Ibm Associative array

Also Published As

Publication number Publication date
IT1042254B (it) 1980-01-30
FR2331121A1 (fr) 1977-06-03
US3992704A (en) 1976-11-16
DE2443529A1 (de) 1976-03-25
NL7510186A (nl) 1976-03-15
GB1522183A (en) 1978-08-23
CH586946A5 (fr) 1977-04-15
DE2443529C3 (fr) 1978-04-27
DE2443529B2 (de) 1977-09-01

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