NL7113561A - - Google Patents

Info

Publication number
NL7113561A
NL7113561A NL7113561A NL7113561A NL7113561A NL 7113561 A NL7113561 A NL 7113561A NL 7113561 A NL7113561 A NL 7113561A NL 7113561 A NL7113561 A NL 7113561A NL 7113561 A NL7113561 A NL 7113561A
Authority
NL
Netherlands
Application number
NL7113561A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to NL7113561A priority Critical patent/NL7113561A/xx
Priority to GB4510172A priority patent/GB1400865A/en
Priority to CH1424272A priority patent/CH546008A/xx
Priority to IT70082/72A priority patent/IT975127B/it
Priority to ES407201A priority patent/ES407201A1/es
Priority to DE19722248198 priority patent/DE2248198A1/de
Priority to JP47098077A priority patent/JPS5112991B2/ja
Priority to FR7234816A priority patent/FR2154778B1/fr
Priority to US00293782A priority patent/US3852104A/en
Publication of NL7113561A publication Critical patent/NL7113561A/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
NL7113561A 1971-10-02 1971-10-02 NL7113561A (enExample)

Priority Applications (9)

Application Number Priority Date Filing Date Title
NL7113561A NL7113561A (enExample) 1971-10-02 1971-10-02
GB4510172A GB1400865A (en) 1971-10-02 1972-09-29 Semiconductor device manufacture
CH1424272A CH546008A (enExample) 1971-10-02 1972-09-29
IT70082/72A IT975127B (it) 1971-10-02 1972-09-29 Procedimento per la fabbricazione di un dispositivo semiconduttore e dispositivo semiconduttore ot tenuto col procedimento
ES407201A ES407201A1 (es) 1971-10-02 1972-09-30 Un metodo de fabricar un dispositivo semiconductor.
DE19722248198 DE2248198A1 (de) 1971-10-02 1972-10-02 Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte halbleiteranordnung
JP47098077A JPS5112991B2 (enExample) 1971-10-02 1972-10-02
FR7234816A FR2154778B1 (enExample) 1971-10-02 1972-10-02
US00293782A US3852104A (en) 1971-10-02 1972-10-02 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7113561A NL7113561A (enExample) 1971-10-02 1971-10-02

Publications (1)

Publication Number Publication Date
NL7113561A true NL7113561A (enExample) 1973-04-04

Family

ID=19814158

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7113561A NL7113561A (enExample) 1971-10-02 1971-10-02

Country Status (9)

Country Link
US (1) US3852104A (enExample)
JP (1) JPS5112991B2 (enExample)
CH (1) CH546008A (enExample)
DE (1) DE2248198A1 (enExample)
ES (1) ES407201A1 (enExample)
FR (1) FR2154778B1 (enExample)
GB (1) GB1400865A (enExample)
IT (1) IT975127B (enExample)
NL (1) NL7113561A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038290B1 (en) 1965-09-28 2006-05-02 Li Chou H Integrated circuit device
US5696402A (en) * 1965-09-28 1997-12-09 Li; Chou H. Integrated circuit device
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
IN140846B (enExample) * 1973-08-06 1976-12-25 Rca Corp
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
JPS51114079A (en) * 1975-03-31 1976-10-07 Fujitsu Ltd Construction of semiconductor memory device
JPS5293278A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for mos type semiconductor intergrated circuit
US4125427A (en) * 1976-08-27 1978-11-14 Ncr Corporation Method of processing a semiconductor
US4219925A (en) * 1978-09-01 1980-09-02 Teletype Corporation Method of manufacturing a device in a silicon wafer
NL7903158A (nl) * 1979-04-23 1980-10-27 Philips Nv Werkwijze voor het vervaardigen van een veldeffekt- transistor met geisoleerde poortelektrode, en transistor vervaardigd door toepassing van een derge- lijke werkwijze.
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
DE3572086D1 (en) * 1984-12-13 1989-09-07 Siemens Ag Method of producing an isolation separating the active regions of a highly integrated cmos circuit
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
US5656510A (en) 1994-11-22 1997-08-12 Lucent Technologies Inc. Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control
US20040144999A1 (en) * 1995-06-07 2004-07-29 Li Chou H. Integrated circuit device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3425879A (en) * 1965-10-24 1969-02-04 Texas Instruments Inc Method of making shaped epitaxial deposits
US3418227A (en) * 1966-03-31 1968-12-24 Texas Instruments Inc Process for fabricating multiple layer circuit boards
US3578515A (en) * 1967-04-05 1971-05-11 Texas Instruments Inc Process for fabricating planar diodes in semi-insulating substrates
GB1250917A (enExample) * 1967-12-30 1971-10-27
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3706129A (en) * 1970-07-27 1972-12-19 Gen Electric Integrated semiconductor rectifiers and processes for their fabrication
US3796612A (en) * 1971-08-05 1974-03-12 Scient Micro Syst Inc Semiconductor isolation method utilizing anisotropic etching and differential thermal oxidation

Also Published As

Publication number Publication date
IT975127B (it) 1974-07-20
DE2248198A1 (de) 1973-04-05
CH546008A (enExample) 1974-02-15
GB1400865A (en) 1975-07-16
FR2154778A1 (enExample) 1973-05-11
US3852104A (en) 1974-12-03
JPS5112991B2 (enExample) 1976-04-23
JPS4844080A (enExample) 1973-06-25
FR2154778B1 (enExample) 1977-08-26
ES407201A1 (es) 1975-11-01

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