NL6714336A - - Google Patents

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Publication number
NL6714336A
NL6714336A NL6714336A NL6714336A NL6714336A NL 6714336 A NL6714336 A NL 6714336A NL 6714336 A NL6714336 A NL 6714336A NL 6714336 A NL6714336 A NL 6714336A NL 6714336 A NL6714336 A NL 6714336A
Authority
NL
Netherlands
Application number
NL6714336A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to NL6714336A priority Critical patent/NL6714336A/xx
Priority to US767062A priority patent/US3579056A/en
Priority to DE19681803138 priority patent/DE1803138A1/de
Priority to FR1591647D priority patent/FR1591647A/fr
Priority to SE14114/68A priority patent/SE352480B/xx
Priority to GB1250815D priority patent/GB1250815A/en
Priority to CH1565468A priority patent/CH496322A/de
Priority to BR203288/68A priority patent/BR6803288D0/pt
Priority to ES359345A priority patent/ES359345A1/es
Priority to BE722669D priority patent/BE722669A/xx
Publication of NL6714336A publication Critical patent/NL6714336A/xx

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Classifications

    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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NL6714336A 1967-10-21 1967-10-21 NL6714336A (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
NL6714336A NL6714336A (ja) 1967-10-21 1967-10-21
US767062A US3579056A (en) 1967-10-21 1968-10-10 Semiconductor circuit having active devices embedded in flexible sheet
DE19681803138 DE1803138A1 (de) 1967-10-21 1968-10-15 Halbleitervorrichtung
FR1591647D FR1591647A (ja) 1967-10-21 1968-10-17
SE14114/68A SE352480B (ja) 1967-10-21 1968-10-18
GB1250815D GB1250815A (ja) 1967-10-21 1968-10-18
CH1565468A CH496322A (de) 1967-10-21 1968-10-18 Halbleitervorrichtung
BR203288/68A BR6803288D0 (pt) 1967-10-21 1968-10-18 Dispositivo semicondutor e processo para fazer o mesmo
ES359345A ES359345A1 (es) 1967-10-21 1968-10-19 Un dispositivo semiconductor.
BE722669D BE722669A (ja) 1967-10-21 1968-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6714336A NL6714336A (ja) 1967-10-21 1967-10-21

Publications (1)

Publication Number Publication Date
NL6714336A true NL6714336A (ja) 1969-04-23

Family

ID=19801524

Family Applications (1)

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NL6714336A NL6714336A (ja) 1967-10-21 1967-10-21

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US (1) US3579056A (ja)
BE (1) BE722669A (ja)
BR (1) BR6803288D0 (ja)
CH (1) CH496322A (ja)
DE (1) DE1803138A1 (ja)
ES (1) ES359345A1 (ja)
FR (1) FR1591647A (ja)
GB (1) GB1250815A (ja)
NL (1) NL6714336A (ja)
SE (1) SE352480B (ja)

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US5344795A (en) * 1992-09-22 1994-09-06 Microelectronics And Computer Technology Corporation Method for encapsulating an integrated circuit using a removable heatsink support block
DE20117575U1 (de) * 2001-10-26 2002-03-28 Moser Helmut Sandwichplatte mit beidseitigen Leuchtfeldern
DE10153609C2 (de) * 2001-11-02 2003-10-16 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
DE10164800B4 (de) * 2001-11-02 2005-03-31 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
DE10250621B4 (de) * 2002-10-30 2004-09-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Erzeugen verkapselter Chips und zum Erzeugen eines Stapels aus den verkapselten Chips
TW200507131A (en) * 2003-07-02 2005-02-16 North Corp Multi-layer circuit board for electronic device
US7768117B2 (en) * 2007-05-30 2010-08-03 Tessera, Inc. Microelectronic package having interconnected redistribution paths
US8237259B2 (en) 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
US7968378B2 (en) * 2008-02-06 2011-06-28 Infineon Technologies Ag Electronic device
DE102010039156A1 (de) 2010-08-10 2012-02-16 Robert Bosch Gmbh Verfahren zum Herstellen einer elektrischen Schaltung und elektrische Schaltung
DE102010040704A1 (de) 2010-09-14 2012-03-15 Robert Bosch Gmbh Verfahren zum Aufbauen einer elektrischen Schaltung und elektrische Schaltung
DE112012005313A5 (de) 2011-12-19 2015-04-23 Inoviscoat Gmbh Leuchtbild
ES2648364T3 (es) 2011-12-19 2018-01-02 Inoviscoat Gmbh Elementos luminosos con una disposición electroluminiscente así como procedimiento para la producción de un elemento luminoso
DE102012005192A1 (de) * 2011-12-19 2013-06-20 Inoviscoat Gmbh Leuchtbild
US9129959B2 (en) 2012-08-21 2015-09-08 Infineon Technologies Ag Method for manufacturing an electronic module and an electronic module
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Also Published As

Publication number Publication date
BE722669A (ja) 1969-04-21
CH496322A (de) 1970-09-15
ES359345A1 (es) 1970-08-16
GB1250815A (ja) 1971-10-20
SE352480B (ja) 1972-12-27
BR6803288D0 (pt) 1973-01-04
DE1803138A1 (de) 1969-06-04
US3579056A (en) 1971-05-18
FR1591647A (ja) 1970-05-04

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