MY173537A - Manufacturing apparatus and manufacturing method - Google Patents
Manufacturing apparatus and manufacturing methodInfo
- Publication number
- MY173537A MY173537A MYPI2016700554A MYPI2016700554A MY173537A MY 173537 A MY173537 A MY 173537A MY PI2016700554 A MYPI2016700554 A MY PI2016700554A MY PI2016700554 A MYPI2016700554 A MY PI2016700554A MY 173537 A MY173537 A MY 173537A
- Authority
- MY
- Malaysia
- Prior art keywords
- cut
- qfn
- along
- qfn substrate
- substrate
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Dicing (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A QFN substrate (2) is cut at three stages along a plurality of cutting lines (9, 10) set in a grid pattern in the QFN substrate (2). First, on the cutting lines (9) along the longer direction of the QFN substrate (2), a portion substantially corresponding to a thickness of a tie bar (6) of a lead frame (2) is cut, thereby forming cut trenches (23). Next, on the cutting lines (10) along the shorter direction of the QFN substrate (2), the lead frame (2) and a sealing resin (8) are collectively cut. Next, on the cut trenches (23) along the longer direction (9) of the QFN substrate (2), a portion corresponding to a remaining thickness of the sealing resin (8) is cut. Since only the portion of the sealing resin (8) is cut on the cut trenches (23), the processing load when the QFN substrate (2) is finally divided into QFN products (13) can be reduced. Therefore, it is possible to prevent the QFN product (13) from being displaced or scattered from a prescribed position of a cutting jig (15).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015042803A JP6525643B2 (en) | 2015-03-04 | 2015-03-04 | Manufacturing apparatus and manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
MY173537A true MY173537A (en) | 2020-02-03 |
Family
ID=56847225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MYPI2016700554A MY173537A (en) | 2015-03-04 | 2016-02-17 | Manufacturing apparatus and manufacturing method |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP6525643B2 (en) |
KR (1) | KR101779701B1 (en) |
CN (1) | CN105938808B (en) |
MY (1) | MY173537A (en) |
TW (1) | TWI618193B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6800745B2 (en) * | 2016-12-28 | 2020-12-16 | 株式会社ディスコ | Semiconductor package manufacturing method |
JP7043346B2 (en) * | 2018-05-18 | 2022-03-29 | 株式会社ディスコ | Cutting equipment |
JP2020088262A (en) * | 2018-11-29 | 2020-06-04 | 株式会社ディスコ | Division method of package substrate |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2592489B2 (en) * | 1988-03-18 | 1997-03-19 | 富士通株式会社 | Wafer dicing method |
JPH0574932A (en) * | 1991-09-17 | 1993-03-26 | Fujitsu Ltd | Dicing method for semiconductor wafer |
JP3229035B2 (en) * | 1992-09-25 | 2001-11-12 | ローム株式会社 | Silicon wafer cutting method |
JP3521325B2 (en) | 1999-07-30 | 2004-04-19 | シャープ株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
JP2002343817A (en) | 2001-05-11 | 2002-11-29 | Tomoegawa Paper Co Ltd | Semiconductor device unit |
JP2003031526A (en) * | 2001-07-16 | 2003-01-31 | Mitsumi Electric Co Ltd | Module and manufacturing method thereof |
JP2006222359A (en) * | 2005-02-14 | 2006-08-24 | Hitachi Cable Ltd | Manufacturing method of light emitting diode array |
US7694688B2 (en) * | 2007-01-05 | 2010-04-13 | Applied Materials, Inc. | Wet clean system design |
JP2009170501A (en) * | 2008-01-11 | 2009-07-30 | Disco Abrasive Syst Ltd | Cutting apparatus |
JP2011035142A (en) * | 2009-07-31 | 2011-02-17 | Sanyo Electric Co Ltd | Method of manufacturing circuit device |
US8801307B2 (en) * | 2009-09-25 | 2014-08-12 | Nikon Corporation | Substrate cartridge, substrate processing apparatus, substrate processing system, control apparatus, and method of manufacturing display element |
JP2011159679A (en) * | 2010-01-29 | 2011-08-18 | Furukawa Electric Co Ltd:The | Method of manufacturing chip |
JP2011211159A (en) * | 2010-03-10 | 2011-10-20 | Renesas Electronics Corp | Method for manufacturing semiconductor device |
US9349679B2 (en) * | 2010-08-31 | 2016-05-24 | Utac Thai Limited | Singulation method for semiconductor package with plating on side of connectors |
JP5899614B2 (en) * | 2010-11-26 | 2016-04-06 | 大日本印刷株式会社 | Leadframe and leadframe manufacturing method |
JP2013069814A (en) * | 2011-09-21 | 2013-04-18 | Renesas Electronics Corp | Method for manufacturing semiconductor device |
JP5897454B2 (en) * | 2012-12-03 | 2016-03-30 | Towa株式会社 | Cutting apparatus and method for manufacturing electronic parts |
JP6111168B2 (en) * | 2013-08-23 | 2017-04-05 | 株式会社ディスコ | Package substrate division method |
-
2015
- 2015-03-04 JP JP2015042803A patent/JP6525643B2/en active Active
-
2016
- 2016-02-17 MY MYPI2016700554A patent/MY173537A/en unknown
- 2016-02-17 TW TW105104553A patent/TWI618193B/en active
- 2016-03-02 KR KR1020160024826A patent/KR101779701B1/en active IP Right Grant
- 2016-03-04 CN CN201610124832.3A patent/CN105938808B/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2016162973A (en) | 2016-09-05 |
CN105938808A (en) | 2016-09-14 |
CN105938808B (en) | 2018-10-26 |
KR20160108170A (en) | 2016-09-19 |
TW201701409A (en) | 2017-01-01 |
KR101779701B1 (en) | 2017-10-10 |
JP6525643B2 (en) | 2019-06-05 |
TWI618193B (en) | 2018-03-11 |
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