MY131022A - Silicon wafers having controlled distribution of defects, and methods of preparing the same - Google Patents

Silicon wafers having controlled distribution of defects, and methods of preparing the same

Info

Publication number
MY131022A
MY131022A MYPI20012486A MY131022A MY 131022 A MY131022 A MY 131022A MY PI20012486 A MYPI20012486 A MY PI20012486A MY 131022 A MY131022 A MY 131022A
Authority
MY
Malaysia
Prior art keywords
wafer
peaks
bottom surfaces
defects
controlled distribution
Prior art date
Application number
Inventor
Park Jea-Gun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2000-0057344A external-priority patent/KR100378184B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of MY131022A publication Critical patent/MY131022A/en

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

A SILICON WAFER IS PROVIDED HAVING CONTROLLED DISTRIBUTION OF DEFECTS, IN WHICH DENUDED ZONES HAVING A SUFFICIENT DEPTH INWARD FROM THE SURFACE OF THE WAFER ARE COMBINED WITH A HIGH GETTERING EFFECT IN A BULK REGION OF THE WAFER, IN THE SILICON WAFER, OXYGEN PRECIPITATES, WHICH ACT AS INTRINSIC GETTERING SITES, SHOW VERTICAL DISTRIBUTION.THE OXYGEN PRECIPITATE CONCENTRATION PROFILE FROM THE TOP TO THE BOTTOM SURFACES OF THE WAFER INCLUDES FIRST AND SECOND PEAKS AT FIRST AND SECOND PREDETERMINED DEPTHS FROM THE TOP AND BOTTOM SURFACES OF THE WAFER, DENUDED ZONES BETWEEN THE TOP AND BOTTOM SURFACES OF THE WAFER AND EACH OF THE FIRST AND SECOND PEAKS, AND A CONCAVE REGION BETWEEN THE FIRST AND SECOND PEAKS, WHICH CORRESPONDS TO A BULK REGION OF THE WAFER.FOR SUCH AN OXYGEN PRECIPITATE CONCENTRATION PROFILE, THE WAFER IS EXPOSED TO A RAPID THERMAL ANNEALING PROCESS IN A GAS MIXTURE ATMOSPHERE CONTAINING NITROGEN (N2) AND ARGON (Ar) OR N2 AND HYDROGEN (H2), AN A DONOR KILLING STEP DURING A WAFERING PROCESS.(FIG 4)
MYPI20012486 2000-09-29 2001-05-24 Silicon wafers having controlled distribution of defects, and methods of preparing the same MY131022A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2000-0057344A KR100378184B1 (en) 1999-11-13 2000-09-29 Silicon wafer having controlled distribution of defects, process for the preparation of the same and czochralski puller for manufacturing monocrystalline silicon ingot

Publications (1)

Publication Number Publication Date
MY131022A true MY131022A (en) 2007-07-31

Family

ID=36772732

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI20012486 MY131022A (en) 2000-09-29 2001-05-24 Silicon wafers having controlled distribution of defects, and methods of preparing the same

Country Status (4)

Country Link
CN (2) CN1289720C (en)
IT (1) ITMI20011120A1 (en)
MY (1) MY131022A (en)
SG (2) SG108822A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4853027B2 (en) * 2006-01-17 2012-01-11 信越半導体株式会社 Method for producing silicon single crystal wafer
TWI580825B (en) * 2012-01-27 2017-05-01 Ｍｅｍｃ新加坡有限公司 Method of preparing cast silicon by directional solidification
JP6100226B2 (en) * 2014-11-26 2017-03-22 信越半導体株式会社 Heat treatment method for silicon single crystal wafer
KR101759876B1 (en) * 2015-07-01 2017-07-31 주식회사 엘지실트론 Wafer and method for analyzing defect of the wafer
JP6254748B1 (en) * 2016-11-14 2017-12-27 信越化学工業株式会社 High photoelectric conversion efficiency solar cell manufacturing method and high photoelectric conversion efficiency solar cell

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63315589A (en) * 1987-06-16 1988-12-23 Osaka Titanium Seizo Kk Single crystal production apparatus
FI901414A0 (en) * 1989-03-30 1990-03-21 Nippon Kokan Kk ANORDINATION FOR FRAMING A KISELENKRISTALLER.
EP0494307A4 (en) * 1990-03-20 1992-10-14 Nkk Corporation Apparatus for making silicon single crystal
US5401669A (en) * 1993-05-13 1995-03-28 Memc Electronic Materials, Spa Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
JPH0761889A (en) * 1993-08-26 1995-03-07 Komatsu Electron Metals Co Ltd Semiconductor single crystal pull device and method fir pulling semiconductor single crystal
JPH1179889A (en) * 1997-07-09 1999-03-23 Shin Etsu Handotai Co Ltd Production of and production unit for silicon single crystal with few crystal defect, and silicon single crystal and silicon wafer produced thereby
JP3992800B2 (en) * 1997-09-22 2007-10-17 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Single crystal manufacturing apparatus and single crystal manufacturing method
JP4166316B2 (en) * 1998-02-27 2008-10-15 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Single crystal manufacturing equipment
JP3670493B2 (en) * 1998-10-09 2005-07-13 東芝セラミックス株式会社 Single crystal pulling device
JP3709494B2 (en) * 1999-02-26 2005-10-26 株式会社Ｓｕｍｃｏ Heat shielding member of silicon single crystal pulling device
US6197111B1 (en) * 1999-02-26 2001-03-06 Memc Electronic Materials, Inc. Heat shield assembly for crystal puller

Also Published As

Publication number Publication date
ITMI20011120A0 (en) 2001-05-25
CN100430531C (en) 2008-11-05
SG108822A1 (en) 2005-02-28
ITMI20011120A1 (en) 2002-11-25
CN1345986A (en) 2002-04-24
CN1289720C (en) 2006-12-13
SG135030A1 (en) 2007-09-28
CN1782140A (en) 2006-06-07

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