CN1289720C

CN1289720C - Silicon wafe with controlled defect distribution, its making method and caochralski pulling machine

Info

Publication number: CN1289720C
Application number: CN 01123301
Authority: CN
Inventors: 朴在勤
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2000-09-29
Filing date: 2001-05-25
Publication date: 2006-12-13
Anticipated expiration: 2021-05-25
Also published as: ITMI20011120A1; CN100430531C; SG135030A1; MY131022A; CN1345986A; CN1782140A; ITMI20011120A0; SG108822A1

Abstract

A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and second peaks, which corresponds to a bulk region of the wafer. For such an oxygen precipitate concentration profile, the wafer is exposed to a rapid thermal annealing process in a gas mixture atmosphere containing nitrogen (N2) and argon (Ar) or N2 and hydrogen (H2), in a donor killing step during a wafering process.

Description

Silicon wafer and method for making thereof with controlled defect distribution

Technical field

The present invention relates to the microelectronics manufacturing method and apparatus, more specifically, relate to the silicon ingot and the wafer of the manufacture method of silicon ingot and method manufacturing thus.

Background technology

Grow into the column crystal ingot as the raw-material silicon single crystal of making semiconductor device by crystal technique, this technology is called as (CZ) technology of caochralski (Czochralski).The crystal ingot of silicon single crystal is through becoming wafer such as a series of wafer process processes such as section, etching, cleaning, polishings.According to the CZ technology, the seed crystal of silicon single crystal immerses molten silicon and upwards lifts, and molten silicon grows into single crystal rod by separating at a slow speed then.Molten silicon is contained in the quartz crucible, is subjected to the pollution of various impurity, and wherein a kind of is oxygen.Under the melt temperature of silicon, oxygen infiltrates lattice up to reaching predetermined concentration, and this concentration is determined by solubleness and oxygen the actual segregation coefficient in solidification of silicon of oxygen under the silicon melt temperature in silicon usually.Be higher than at semiconductor device at the oxygen concn that infiltrates silicon ingot during the crystal growth and make the oxygen solubility in the solidification of silicon under the employed representative temperature.When crystal was grown from molten silicon and cooled off, oxygen solubility wherein reduced rapidly, thereby oxygen is saturated in the refrigerative crystal ingot.This crystal ingot is cut into wafer.Interstitial oxygen concentration remaining in each wafer is grown into the oxygen deposition thing in subsequent heat treatment.The existence of oxygen deposition thing reduces the integrity of gate oxide and partly causes substrate leakage stream in the device active region.Yet when active region (main body) that they appear at device in addition the time, they can be caught from the metallic impurity in the device processing; This is called as capture effect.

Fig. 1 is the transistorized sectional view of common metal oxide semiconductor (MOS).With reference to Fig. 1, when the oxygen deposition thing on the wafer surface is present in when being formed near the channel region in the active region of the source area 12 on the surface of silicon substrate 10 and the semiconductor device between the drain region 14, be used for the gate insulation layer 16 of gate electrode 18 and silicon substrate 10 electrical isolations may be punctured.In addition, adopt the refreshing characteristic and may reduce of storing device of MOSFET.

In addition, be formed among the wafer body region 10a by subsequent heat treatment produce the oxygen deposition thing can serve as source of leaks (leakage source), also can serve as intrinsic and catch the position, they can catch harmful metal impurity in follow-up semiconductor device fabrication.So, if the oxygen concn height in the crystal ingot serves as intrinsic and catches the concentration of the oxygen deposition thing of position and increase, so capture ability improves.But if oxygen concn is not enough, the oxygen deposition thing can not produce in body region so, so capture ability can reduce or not existence.Thereby, wish that suitably control is distributed in the amount of the oxygen deposition thing in the wafer body region.

In the wafer that obtains by conventional crystal growth and wafer process technology, the oxygen deposition thing is distributed in from pushing up (front side) face on earth the entire wafer of (rear side) face.Generally speaking, should provide (DZ) 10b of a stripping section (Denuded Zone) from end face to predetermined depth, it does not contain D-defective (accumulation of vacancies), dislocation, fault and oxygen deposition thing etc.But the wafer of being made by traditional method can produce the oxygen deposition thing near wafer surface, and it can serve as the source of leakage current.

Thereby, catch the position in order in the body region of the wafer that sufficient DZ is arranged near wafer surface, to form intrinsic, wafer with hyperoxia concentration, for example, per 1,000,000 atoms (ppma) contain the wafer of 13 parts or more initial oxygen concentration, can carry out long thermal treatment by the temperature that changes between lower bound and the high limit, so the oxygen deposition thing can generate in the body region of wafer, yet, be difficult to obtain enough DZ, be because DZ depend on consumingly interstitial oxygen concentration to external diffusion.In by the heat treated semiconductor wafer of conventional art, the distribution of oxygen deposition substrate concentration from the end face of wafer to the entire wafer of bottom surface as shown in Figure 2.

Particularly, adopt the heat treated conventional art of additional high temperature of long period can reduce equipment energy characteristic.For example, in wafer slippage or distortion may take place.In addition, manufacturing cost will increase.In addition, in this case, by the metallic impurity of being caught by oxygen deposition thing in the body region, especially iron (Fe) can be discharged among the DZ by subsequent disposal, thereby the impurity that is discharged can serve as source of leaks.

Fig. 3 is the figure that shows the tempering oxygen deposition concentration profile of the wafer of being made by another traditional method, and this method is disclosed in U.S. Patent No. 5,401, among Figure 1A of 669.Particularly, Fig. 3 is that the oxygen deposition substrate concentration is with respect to the distribution of wafer depth in the wafer, and this comes from the wafer rapid thermal anneal process of implementing in the nitrogen environment, and makes this wafer stand subsequent heat treatment.But, as seeing, both cannot obtain DZ near wafer surface by this traditional method from Fig. 3, also cannot obtain competent oxygen deposition thing.

Summary of the invention

Embodiments of the invention provide a kind of silicon wafer with the controlled vertical distribution of oxygen deposition thing, and this oxygen deposition thing can serve as intrinsic and catch the position.Particularly, the oxygen deposition concentration profile from the end face that can form the semiconductor device active region to the bottom surface of silicon wafer is comprising first and second peak values from the end face of wafer and first and second predetermined depths of bottom surface respectively.Also comprising a stripping section (DZ) between the end face of wafer and first peak value and between the bottom surface of wafer and second peak value.This oxygen deposition concentration profile also has a recessed district between first and second peak values, it can be corresponding to the body region of wafer.

In an embodiment of the present invention, the oxygen deposition concentration profile is about being centrally placed in the silicon wafer median plane symmetry between top and bottom.Thereby for example, first and second predetermined depths are identical.But in other embodiments, this distribution needn't be symmetrical, therefore, for example, for first and second peak values different degree of depth can be arranged.Equally, in some embodiments of the invention, the degree of depth of stripping section is from the scope of about 10 μ m to the 40 μ m in two surfaces of silicon wafer, makes the active region of semiconductor device form enough degree of depth.In other embodiments, the lattice defect relevant with oxygen is not present among the DZ, and has the D defective that predetermined size exists with the hole form, and the oxygen deposition thing, can further be present in the body region of wafer with predetermined concentration.

In another embodiment of the present invention, the oxygen deposition substrate concentration at the first and second peak value places is at least about 1 * 10 ⁹Cm ^-3, and the oxygen deposition substrate concentration in the body region between first and second peak values is at least about 1 * 10 ⁸Cm ^-3

Silicon wafer according to other embodiments of the present invention comprises the controlled distribution such as oxygen deposition thing nucleating centers such as rooms, and these rooms can produce aforesaid oxygen deposition concentration profile by subsequent heat treatment.Vacancy concentration comprises and being in respectively apart from the end face of wafer and first and second peak values of bottom surface first and second predetermined depths.And, this vacancy concentration remain on than on the low predetermined concentration of threshold concentration to form the DZ district between the end face of wafer and first peak value and between the bottom surface of wafer and second peak value.At last, this vacancy concentration has recessed district between first and second peak values.Symmetry or asymmetric distribution can be provided.

The method according to this invention embodiment, comprising gas and on the end face of silicon wafer and bottom surface, having in the environment of gaseous mixture of gas of gap silicon injection effect with room injection effect, silicon wafer is implemented rapid thermal annealing (RTA), to produce the nucleating center, oxygen deposition thing growth position is served as at this center in subsequent heat treatment, thereby the concentration distribution of the nucleating center from wafer top surface to the bottom surface comprises first and second peak values respectively in the end face and bottom surface first and second predetermined depths of distance wafer.And, the concentration of this nucleating center remain on than on the low predetermined concentration of threshold concentration to form the DZ district between the end face of wafer and first peak value and between the bottom surface of wafer and second peak value.At last, the concentration distribution of this nucleating center has recessed district between first and second peak values, and this district is corresponding to the body region of wafer.Symmetry or asymmetric distribution can be provided.

According to other method embodiment, after RTA, implement thermal treatment, generating the oxygen deposition concentration profile from the wafer top surface to the bottom surface, this distribution comprises respectively at first and second peak values at the end face of distance wafer and the first and second predetermined depth places, bottom surface, between the end face of wafer and first peak value and bottom surface and the DZ between second peak value and the recessed district between first and second peak values of wafer.Symmetry or asymmetric distribution can be provided.

In other embodiments of the invention, gaseous mixture comprises nitrogen (N ₂) gas and argon (Ar) gas, perhaps nitrogen (N ₂) gas and hydrogen (H ₂) gas.In addition, in an embodiment of the present invention, the oxygen deposition substrate concentration in place, first and second peaks and body region and/or the stripping section degree of depth can be controlled by at least one item in ratio of mixture, mixed gas flow velocity, temperature rise rate (ramp-up rate), annealing temperature, annealing time and the rate of temperature fall (ramp-down rate) in the adjustment RTA process.

In an embodiment of the present invention, stood to make with crystal ingot according to the silicon wafer of the RTA process of the embodiment of the invention, this crystal ingot is according to pulling out in the molten silicon of crystal ingot rate of pulling distribution from hot-zone smelting furnace (hot zonefurnace), at this, the crystal ingot rate of pulling is enough high to prevent that the gap accumulative from forming, and is limited in the district of axial rich room, crystal ingot center with the formation with accumulation of vacancies but enough hang down again.

In other embodiments of the invention, stood to make with crystal ingot according to the silicon wafer of the RTA process of the embodiment of the invention, this crystal ingot is according to pulling out in the molten silicon of crystal ingot rate of pulling distribution from the smelting furnace of hot-zone, at this, the crystal ingot rate of pulling is enough high to prevent that the gap accumulative from forming, but enough low again preventing that the gap accumulative from forming, and prevent the formation of accumulation of vacancies.

In other embodiment of the present invention, stood to make with crystal ingot according to the silicon wafer of the RTA process of the embodiment of the invention, this crystal ingot is according to pulling out in the molten silicon of crystal ingot rate of pulling distribution from the smelting furnace of hot-zone, at this, the enough height of the crystal ingot rate of pulling are not assembled and do not form the gap so that accumulation of vacancies forms on the diameter of crystal ingot.

According to other embodiments of the invention, the czochralski pullers that is used for the growing single-crystal silicon ingot comprises the chamber big envelope, holds the crucible of molten silicon at this chamber big envelope, be used for the sub brilliant anchor clamps of clamping seed crystal near the crucible place and at the well heater of this chamber big envelope around crucible in this chamber big envelope.In this chamber big envelope, also is furnished with annular insulation plate, it comprises mutual isolated thermal insulation cover wall, and at the bottom of the insulation plate that links to each other with thermal insulation cover wall top and the insulation plate, the top of insulation plate is from the upward outside thermoscreen cover wall of interior insulation plate wall, and the end of insulation plate insulation plate wall outside interior insulation plate wall is oblique downwards.Support component is supported on this insulation plate in the crucible.

Czochralski pullers according to the embodiment of the invention is also pulled out seed holder from crucible, molten silicon is grown into the column silicon single crystal ingot, this silicon ingot is grown along also centering on its columniform central shaft, and forms crystal ingot-molten silicon interface with molten silicon.Distance between oblique angle, crystal ingot and the interior insulation plate wall of the thermal insulation cover wall length of insulation plate, insulation plate T﹠B, crucible and outside select at least one in the position of distance between distance, molten silicon and the interior insulation plate wall between the insulation plate wall and thermal baffle, make the crystal ingot pull out based on the temperature at crystal ingot center, be cooled to the preset temp of crystal ingot from the temperature at crystal ingot-molten silicon interface with the speed of at least 1.4 ° of K/min.

Thereby, according to embodiments of the invention, wafer stands RTA in the gaseous mixture environment, and then cause in the distribution that has the oxygen deposition thing nucleating center of two peak values from each surperficial predetermined depth place of wafer, wherein gaseous mixture is included in the gas that the gas of gap injection effect is provided and the room injection effect is provided on this wafer.

In addition, embodiment according to RTA process of the present invention carries out at the atmosphere surrounding that provides the gap to inject effectiveness, though make in wafer, to exist that the D-defective can be dissolved within the degree of depth of DZ, so that clean active region is provided in semiconductor device such as the such hole of D-defective.

In addition, can cool off the crystal ingot of pulling out fast, therefore can do forr a short time in the size in the hole that the crystal ingot growing period forms according to the embodiment of czochralski pullers of the present invention.This little hole that appears among the DZ can be via the RTA process dissolving according to the embodiment of the invention, and the hole is retained in the body region of wafer simultaneously.

The size that is formed at the accumulation of vacancies in the silicon wafer in lifting step is about 0.2 μ m.

Description of drawings

Fig. 1 is the sectional view that is presented at the transistorized structure of conventional metals oxide semiconductor (MOS) that forms near silicon wafer surface;

Fig. 2 is the figure that shows the oxygen deposition concentration profile of conventional wafer;

Fig. 3 is the figure that shows the oxygen deposition concentration profile of another conventional wafer;

Fig. 4 illustrates the oxygen deposition concentration profile according to the silicon wafer of the embodiment of the invention;

Fig. 5 is the time diagram that is used for rapid thermal annealing (RTA) according to the embodiment of the invention;

Fig. 6 illustrates RTA process shown in Figure 5 at nitrogen (N ₂) implement in the compression ring border after, distribute with respect to the point defect concentration of wafer depth;

Fig. 7 illustrates RTA process shown in Figure 5 in argon (Ar) compression ring border, implement after, distribute with respect to the point defect concentration of wafer depth;

Fig. 8 illustrates RTA process shown in Figure 5 at hydrogen (H ₂) implement in the compression ring border after, distribute with respect to the point defect concentration of wafer depth;

After Fig. 9 illustrates RTA process shown in Figure 5, with respect to comprising N ₂The vacancy concentration that the blending ratio of the gaseous mixture of gas and Ar gas changes;

Figure 10 illustrates by after the RTA process according to the embodiment of the invention, by the oxygen deposition concentration distribution with respect to all gases that uses during RTA that subsequent heat treatment obtained;

Figure 11 shows when the RTA of Fig. 5 implements in Ar compression ring border, near the dissolving of the primary precipitation thing of the crystal of silicon wafer surface (COP).

Figure 12 shows to have experienced according to the embodiment of the invention at N ₂The photo that the oxygen deposition thing of the wafer of the subsequent heat treatment after the RTA process in the compression ring border distributes;

Figure 13 shows to have experienced the photo that the oxygen deposition thing according to the wafer of the subsequent heat treatment after the RTA process of the embodiment of the invention in Ar compression ring border distributes;

Figure 14 shows to have experienced according to the embodiment of the invention at H ₂The photo that the oxygen deposition thing of the wafer of the subsequent heat treatment after the RTA process in the compression ring border distributes;

Figure 15 shows to have experienced according to the embodiment of the invention at N ₂The photo that distributes with the oxygen deposition thing of the wafer of subsequent heat treatment after the RTA process in the Ar compression ring border;

Figure 16 shows to have experienced according to the embodiment of the invention at N ₂And H ₂The photo that the oxygen deposition thing of the wafer of the subsequent heat treatment after the RTA process in the compression ring border distributes;

Figure 17 shows to have experienced according to the embodiment of the invention at N ₂Near the photo of the degree of depth of the DZ that forms the wafer surface of the subsequent heat treatment after the RTA process in the compression ring border;

Figure 18 is the photo that shows the degree of depth of the DZ that forms the wafer surface that has experienced according to the subsequent heat treatment after the RTA process of the embodiment of the invention in Ar compression ring border near;

Figure 19 shows to have experienced according to the embodiment of the invention at H ₂Near the photo of the degree of depth of the DZ that forms the wafer surface of the subsequent heat treatment after the RTA process in the compression ring border;

Figure 20 shows to have experienced according to the embodiment of the invention at N ₂Near and the photo of the degree of depth of the DZ that forms the wafer surface of the subsequent heat treatment after the RTA process in the Ar compression ring border;

Figure 21 shows to have experienced according to the embodiment of the invention at N ₂And H ₂Near the photo of the degree of depth of the DZ that forms the wafer surface of the subsequent heat treatment after the RTA process in the compression ring border;

Figure 22 A is the photo that shows the COP shape that is in primary (as-grown) state, and Figure 22 B illustrates according to the embodiment of the invention at N ₂The shape of the COP that has changed after the RTA process in the compression ring border;

Figure 23 A is the photo that shows the COP shape that is in primordial condition, and Figure 23 B illustrates according to the embodiment of the invention at N ₂Shape with the COP that has changed after the RTA process in the Ar compression ring border;

Figure 24 A is the photo that shows the COP shape that is in primordial condition, and Figure 24 B illustrates according to the embodiment of the invention at N ₂And H ₂The shape of the COP that has changed after the RTA process in the compression ring border;

Figure 25 is the schema that shows according to the wafer preparation of the embodiment of the invention;

Figure 26 shows that corresponding point defect distribution and V/G are than the synoptic diagram of relation between (crystal ingot is pulled out speed/thermograde) in the silicon ingot;

Figure 27 shows that traditional caochralski (CZ) lifts the sketch of device;

Figure 28 lifts the sketch of device according to another traditional C Z of patent application serial numbers 09/989,591 and 09/320,210;

Figure 29 shows the sketch that lifts device according to the CZ of the embodiment of the invention;

Figure 30 shows that the CZ of Figure 29 lifts the figure of device main part;

Figure 31 is that peak value place oxygen deposition substrate concentration changes with respect to N after the RTA process of Fig. 5 ₂The figure of gas and Ar oxygen mixture change in flow;

Figure 32 is that peak value place oxygen deposition substrate concentration changes with respect to N after the RTA process of Fig. 5 ₂The figure that gas and Ar oxygen mixture ratio of mixture change;

Figure 33 is that peak value place oxygen deposition substrate concentration changes the figure that changes with respect to temperature rise rate after the RTA process of Fig. 5;

Figure 34 is that peak value place oxygen deposition substrate concentration changes the figure that changes with respect to annealing time after the RTA process of Fig. 5;

Figure 35 is that peak value place oxygen deposition substrate concentration changes the figure that changes with respect to annealing temperature after the RTA process of Fig. 5; And

Figure 36 is that peak value place oxygen deposition substrate concentration changes the figure that changes with respect to rate of temperature fall after the RTA process of Fig. 5.

Embodiment

Below with reference to the accompanying drawing that the preferred embodiment of the present invention is shown the present invention is described more fully.But the present invention can implement with various form, and should not be considered to be subject to the embodiment that goes out mentioned herein; More properly, it is in order thoroughly and fully to disclose the present invention that these embodiment are provided, and fully scope of the present invention is pass on to those skilled in the art and provided.In the accompanying drawing, for clarity sake the thickness in floor and district is exaggerated.Identical Reference numeral refers to components identical all the time.Should be understood that when a element such as floor, district or substrate etc. be called as another element " on " time, it can be located immediately on other element, and the existence of intermediary element (intervening element) perhaps also can be arranged.On the contrary, in the time of on an element is called as " directly existing " another element, then without any intermediary element.In addition, each embodiment described herein and illustrated comprises its complementary conduction type (complementary conductivity type) embodiment too.

The simple oxygen deposition concentration profile that shows according to a silicon wafer of the embodiment of the invention of Fig. 4.With the oxygen deposition concentration profile of this distribution and Fig. 2 and the silicon wafer made from conventional art shown in Figure 3 relatively, in the predetermined depth scope of wafer T﹠B face, have stripping section (DZ), and the border of oxygen deposition substrate concentration between each DZ and body region forms bimodal.And, in the body region between bimodal, there are a large amount of oxygen deposition things, this is enough to produce the capture effect to metallic impurity.

Fig. 5 is the time diagram that is used for rapid thermal annealing (RTA) according to the embodiment of the invention.Can use commercial RTA stove.In the RTA process, the RTA stove of at first will silicon wafer according to the present invention packing into, the temperature of this stove (I) during standby is set in for example about 700 ℃.Then, with the speed of for example about 50 ℃/sec the temperature in the RTA stove is elevated to the temperature of about 1250 ℃ (II) rapidly.Then, temperature is remained on one period scheduled time (III) in 1250 ℃ of for example about 10 seconds, and the temperature in the RTA stove is reduced to the temperature of (IV) during the standby with the speed of about 33 ℃/sec rapidly.At last wafer is taken out (V) from the RTA stove.By the embodiment of RTA process shown in Figure 5, the distribution of oxygen deposition thing nucleating center can Be Controlled, and as will be in the back with reference to the narration that Figure 11 did, the hole or the primary precipitation thing of crystal (COP) that occur near the wafer surface can be dissolved.

The temperature ranges of Fig. 5 only is illustrative.Yet, as described below, in RTA according to the embodiment of the invention, blending ratio, temperature rise rate, annealing temperature, annealing time and/or the rate of temperature fall of the kind of environmental gas, the flow velocity of environmental gas, environmental gas (rate of cooling also promptly) all can help obtaining the distribution according to Fig. 4.RTA carries out at least about 5 seconds under at least about 1150 ℃ temperature.For example, RTA carried out 30 seconds under 1150 ℃ temperature at least, perhaps carried out under 1250 ℃ temperature at least 5 to 10 seconds.In addition, wafer cools off rapidly with the speed of at least 30 ℃/sec.

Comprise the gaseous mixture of gas that the gas of room injection effect is provided and gap silicon injection effect is provided to wafer surface as gas according to the RTA of the embodiment of the invention.In certain embodiments, nitrogen (N ₂) gas is as having the gas of room injection effect, argon (Ar) gas and/or hydrogen (H ₂) gas is as having the gas of gap silicon injection effect.

Fig. 6 to Fig. 8 is illustrated in RTA process shown in Figure 5 respectively respectively at N ₂, Ar and H ₂After implementing in the environment, the point defect concentration of the vacancy defect of wafer depth and gap defect silicon distributes relatively.In Fig. 6 to Fig. 8, curve (a) the representative room point defect concentration behind the RTA in inert gas environment distributes, and curve (b) and (c) represent room behind the RTA and the distribution of gap point defect concentration in corresponding atmosphere surrounding respectively.

Shown in the embodiment of Fig. 6 to Fig. 8, the room point defect concentration in inert gas environment after the RTA (convex curve that is indicated by (a)) is low at the end face and the basal surface of wafer, and at the body region height of wafer.When in inert gas environment, when the temperature of RTA stove rapidly increased to the temperature of Fig. 5 mid point (a), the equilibrium concentration in the room that exists as the point defect in the wafer increased.Because the mobility in room is low in the wafer body region, so vacancy concentration keeps below the equilibrium concentration in the body region.But the motion in room is active near wafer surface, so near the vacancy concentration the wafer surface reaches equilibrium concentration rapidly.On the other hand, when the temperature of RTA stove increases sharply, with the increase of vacancy concentration, the equilibrium concentration of gap silicon by the Frank between for example room and the gap silicon you (Frenkel) is compound reduces.In addition, owing to the mobility in the gap that is present in the wafer body region is low, as room herein, the gap concentration in the body region is kept above equilibrium concentration.Yet, reach equilibrium concentration near the gap concentration of wafer surface, as vacancy concentration near wafer surface.

When wafer at high temperature kept one period that reaches Fig. 5 point (b), diffusion took place, and makes room and gap all reach equilibrium concentration.After wafer was cooled to the temperature of Fig. 5 point (c) rapidly, gap point defect with high spread coefficient was issued to a new equilibrium concentration in the temperature that has reduced.Yet, have room point defect supersaturation in wafer of low spread coefficient.Particularly, the degree of supersaturation in room is high in the wafer body region.But, because the mobility in room is near wafer surface place height, so the room point defect concentration reaches new equilibrium concentration immediately under the temperature that has reduced.

Thereby the vacancy concentration in inert gas environment after the RTA has as Fig. 6 to convex shown in Figure 8.

In addition, as shown in Figure 6, at the RTA of Fig. 5 at N ₂Under the situation of carrying out in the compression ring border, be penetrated into the N of wafer body region ₂Gas combines with room silicon, to have formed undersized silicon nitride (Si ₃N ₄), thereby the vacancy concentration in the body region reduces.Simultaneously, because by N ₂The room injection effect of gas is near the vacancy concentration increase of wafer surface.Consequently, N ₂Vacancy concentration under the compression ring border has the shape opposite with the distribution in the wafer of making (by the curve of " b " sign) in inert gas environment.

In addition, when the RTA of Fig. 5 process respectively at Ar and the H shown in Fig. 7 and 8 ₂When carrying out in the compression ring border, because gap silicon injection effect, the vacancy concentration of entire wafer reduces.Particularly, because gases used gap silicon injection effect causes room silicon and being compounded near wafer surface of gap silicon to be taken place rapidly, so vacancy concentration can remain on a threshold concentration, this threshold concentration is the equilibrium concentration under the specified temp.

In an embodiment of the present invention, the RTA of Fig. 5 is such as N ₂Gas and Ar gas or N ₂Gas and H ₂Carry out in the such gaseous mixture environment of gas, and therefore the vacancy concentration under these gaseous mixture environment can distribute and those distributions of Fig. 6 and 8 obtain by those of constitutional diagram 6 and 7.As shown in Figure 9, the vacancy concentration of the wafer of making in this gaseous mixture environment shows first and second peaks from silicon wafer end face and bottom surface predetermined depth place.In addition, can notice that the vacancy concentration from end face and bottom surface to first and second peaks is lower than the equilibrium concentration under the specified temp.In addition, in the first and second peak-to-peak body region, vacancy concentration has recessed shape.

The vacancy concentration of Fig. 9 can obtain according to the embodiment of the invention, and reason is that the RTA process of Fig. 5 is carried out in the gaseous mixture environment that comprises the gas that room and gap silicon injection effect are provided.The use logarithmically calibrated scale will be from N ₂The room silicon concentration that room silicon injection effect in the compression ring border obtains distribute with from Ar or H ₂The gap silicon concentration that gap silicon injection effect in the compression ring border obtains distributes and compares, from the end face of wafer and bottom surface to the zone of predetermined depth, room silicon concentration distribution ratio gap silicon concentration distributes milder.But from the predetermined depth to the body region, silicon concentration the distribute ratio gap silicon concentration that becomes in room distributes more precipitous.Therefore in the stripping section near the end face of wafer and bottom surface, by compound with gap silicon, the room silicon concentration remains on or is lower than a threshold value,, is less than or equal to the equilibrium concentration value of specified temp that is.Outside this stripping section, the room silicon concentration rapidly increases to the value that is equal to or higher than equilibrium concentration.Then, reach the degree of depth place of peaked wafer in the difference of room and gap silicon concentration value, promptly the silicon concentration more precipitous place of ratio gap silicon concentration that becomes that distributes in room has formed peak (first and second peaks).The room silicon concentration is reduced to body region by the place, peak, thereby obtains recessed vacancy concentration between first and second peaks.

According to another embodiment of the present invention, the heat treatment cycle during the room point defect of wafer is made via follow-up semiconductor device produces the oxygen deposition thing.In other words, the room point defect becomes the nucleating center of the oxygen deposition thing that is formed by the subsequent heat treatment circulation.Vacancy concentration is high more, and the oxygen deposition substrate concentration is high more.Therefore can derive the concentration distribution of oxygen deposition thing from the vacancy concentration of wafer.

Vacancy concentration and oxygen deposition substrate concentration have following relationship:

This relational expression shows, as room silicon concentration (V _Si) and initial oxygen concentration (O _i) when increasing, reaction is carried out to the right, thereby the oxygen deposition substrate concentration increases.In above relational expression, σ is a constant.

In an embodiment of the present invention, the wafer of the RTA process that stands Fig. 5 is carried out obtaining the oxygen deposition concentration profile after the subsequent heat treatment.Consider the condition of heat treatment cycle in the semiconductor device manufacturing, the condition of subsequent heat treatment is determined, and the oxygen deposition thing forms in this thermal treatment.In order to compare between wafer, after the RTA of Fig. 5 process, subsequent disposal is at N ₂Carry out about 4 hours at about 800 ℃ in the compression ring border, and carried out about 16 hours at about 1600 ℃.

In addition, in order to investigate the effect of the gaseous mixture that the present invention uses, the flow velocity and the ratio of mixture of the gaseous mixture that uses in the RTA process of Fig. 5 are changed.Fig. 9 comprises N after being illustrated in RTA process shown in Figure 5 relatively ₂The vacancy concentration of the variation of the blending ratio of the gaseous mixture of gas and Ar gas.Figure 31 is the relative Ar/N of peak value display place oxygen deposition substrate concentration ₂The curve of the variation that the mixed gas flow velocity changes.

Among Fig. 9, (a) N is worked as in representative ₂With the ratio of mixture of Ar be 70: 30 o'clock vacancy concentration, (b) N is worked as in representative ₂With the ratio of mixture of Ar be 50: 50 o'clock vacancy concentration, and (c) N is worked as in representative ₂With the ratio of mixture of Ar be 30: 70 o'clock vacancy concentration.Be noted that and work as N ₂When gas concentration increased, the peak moved towards the surface of wafer, and the vacancy concentration at peak increases.That is, the degree of depth of DZ is with N ₂Concentration increases and reduces rapidly, and wherein, the oxygen deposition thing that is caused by subsequent technique does not form in DZ.

Figure 31 at the oxygen deposition substrate concentration at place, peak after the RTA of Fig. 5 finishes, at N ₂Under about 800 ℃, carried out about 4 hours in the compression ring border, carry out about 16 hours further thermal treatment at about 1600 ℃ then and measure after finishing.Here, RTA is by making Ar/N under the condition of the rate of temperature fall of the temperature rise rate of about 50 ℃/sec, about 1250 ℃ annealing temperature, the annealing time in about 10 seconds and about 33 ℃/sec ₂Mixed gas flows and carries out.Ar/N ₂Ar/N in the mixed gas ₂The flow velocity of gas by 1/1,2/2,3/3,4/4 and 5/5l/min change.The result of Figure 31 illustrates the oxygen deposition substrate concentration to be increased with the increase of mixed gas flow velocity.

Remove the Ar/N in the mixed gas ₂Gas is by 3/1, outside the flow velocity of 2.5/1.5,2/2,1.5/2.5 and 1/3l/min provides with various ratio of mixture, and Figure 32 is to measure carry out RTA under the condition identical with the data of Figure 31 after at the oxygen deposition substrate concentration at place, peak.After the RTA of Fig. 5, further thermal treatment is at N ₂Carried out about 4 hours at about 800 ℃ in the compression ring border, then carried out about 16 hours at about 1600 ℃.The result of Figure 32 illustrates, and flows down at the gaseous mixture constant-quality of 4l/min, and the oxygen deposition substrate concentration is along with N in the mixed gas ₂Ratio increase and increase.

The processing condition of RTA, the ratio of mixture and flow velocity, temperature rise rate, annealing temperature and time, the rate of temperature fall etc. that comprise gaseous mixture, can on multiple level, change, with the peak that changes vacancy concentration, the vacancy concentration value at peak value place, the vacancy concentration value of body region, the size and/or the similar value of stripping section.

Figure 33 is presented at that the oxygen deposition substrate concentration at peak value place changes and changes with respect to temperature rise rate after the RTA process of Fig. 5.In order to compare, other processing condition of RTA remain unchanged, that is, and and N ₂The ratio of mixture of gas and Ar gas is set to 50: 50, and annealing temperature is set to 1250 ℃, and annealing time was set to for 10 seconds, and rate of temperature fall is set to 33 ℃/sec.To all wafers, subsequent heat treatment is at N ₂Under 800 ℃ of about 4 hours and thereafter 1600 ℃ of about conditions of 16 hours, carry out in the compression ring border, its with preceding planar survey in identical.It the results are shown in table 1.

Table 1

Temperature rise rate (℃/sec)	Oxygen deposition substrate concentration (the ea/cm at place, peak ³)
Temperature rise rate (℃/sec)		10	2.0×10 ¹⁰
30	2.5×10 ¹⁰	10	2.0×10 ¹⁰
30	2.5×10 ¹⁰	50	2.1×10 ¹⁰
70	2.0×10 ¹⁰	50	2.1×10 ¹⁰
70	2.0×10 ¹⁰	90	2.0×10 ¹⁰

Figure 33 and table 1 show that the oxygen deposition substrate concentration at peak value place is subjected to the influence of temperature rise rate little.

Figure 34 is illustrated in the RTA process variation of the relative annealing time variation of oxygen deposition substrate concentration at peak value place afterwards of Fig. 5.For accurate comparison, other processing condition of RTA remain unchanged, also, and N ₂The ratio of mixture of gas and Ar gas is set to 50: 50, and temperature rise rate is set to 50 ℃/sec, and annealing temperature is set to 1250 ℃, and rate of temperature fall is set to 33 ℃/sec.To all wafers, subsequent heat treatment is at N ₂Under 800 ℃ of about 4 hours and thereafter 1600 ℃ of about conditions of 16 hours, carry out in the compression ring border, its with preceding planar survey in identical.It the results are shown in table 2.

Table 2

Annealing time	Oxygen deposition substrate concentration (the ea/cm at place, peak ³)
Annealing time		1	1.0×10 ⁸
5	5.0×10 ⁹	1	1.0×10 ⁸
5	5.0×10 ⁹	10	2.0×10 ¹⁰
30	2.5×10 ¹⁰	10	2.0×10 ¹⁰
30	2.5×10 ¹⁰	60	3.0×10 ¹⁰

Figure 34 and table 2 show that the oxygen deposition substrate concentration at peak value place is subjected to the influence of annealing time, and for peak value place at least 10 ⁹/ cm ³Or higher oxygen deposition substrate concentration, annealing should continue at least 5 seconds or longer.

Figure 35 is illustrated in the RTA process variation of the relative annealing temperature variation of oxygen deposition substrate concentration at peak value place afterwards of Fig. 5.In order to compare, other processing condition of RTA remain unchanged, also, and N ₂The ratio of mixture of gas and Ar gas is set to 50: 50, and temperature rise rate is set to 50 ℃/sec, and annealing time was set to for 10 seconds, and rate of temperature fall is set to 33 ℃/sec.To all wafers, subsequent heat treatment is at N ₂Under 800 ℃ of about 4 hours and thereafter 1600 ℃ of about conditions of 16 hours, carry out in the compression ring border, its with preceding planar survey in identical.It the results are shown in table 3.

Table 3

Annealing temperature (℃)	Oxygen deposition substrate concentration (the ea/cm at place, peak ³)
Annealing temperature (℃)		1250	2.0×10 ¹⁰
1200	5.0×10 ⁸	1250	2.0×10 ¹⁰
1200	5.0×10 ⁸	1150	1.0×10 ⁸
1100	7.0×10 ⁷	1150	1.0×10 ⁸
1100	7.0×10 ⁷	1000	7.0×10 ⁷

Figure 35 and table 3 show that the oxygen deposition substrate concentration at peak value place is subjected to the influence of annealing temperature, and for peak value place at least 10 ⁹/ cm ³Or higher oxygen deposition substrate concentration, annealing temperature should be high (at least 1250 ℃ or more than).Annealing temperature and time and oxygen deposition substrate concentration are closely connected.Consider the result of Figure 34, can notice that for certain oxygen deposition substrate concentration, annealing time can reduce under higher annealing temperature, yet for certain oxygen deposition substrate concentration, annealing time can prolong under lower annealing temperature.

Figure 36 is illustrated in the variation that the oxygen deposition substrate concentration at peak value place changes with respect to rate of temperature fall after the RTA process of Fig. 5.In order to compare, other processing condition of RTA remain unchanged, also, and N ₂The ratio of mixture of gas and Ar gas is set to 50: 50, and temperature rise rate is set to 50 ℃/sec, and annealing time was set to for 10 seconds.To all wafers, subsequent heat treatment is at N ₂Under 800 ℃ of about 4 hours and thereafter 1600 ℃ of about conditions of 16 hours, carry out in the compression ring border, its with preceding planar survey in identical.It the results are shown in table 4.

Table 4

Rate of temperature fall (℃/sec)	Oxygen deposition substrate concentration (the ea/cm at place, peak ³)
Rate of temperature fall (℃/sec)		10	8.0×10 ⁹
30	2.0×10 ¹⁰	10	8.0×10 ⁹
30	2.0×10 ¹⁰	50	2.2×10 ¹⁰
70	3.0×10 ¹⁰	50	2.2×10 ¹⁰
70	3.0×10 ¹⁰	90	3.5×10 ¹⁰

Figure 36 and table 4 show that the oxygen deposition substrate concentration at peak value place is subjected to the influence of rate of temperature fall little.But the oxygen deposition substrate concentration is along with the increase of temperature rise rate has a little increase.

Figure 10 illustrate by after handling according to the RTA of the embodiment of the invention subsequent heat treatment obtained, with respect to the oxygen deposition concentration profile of using all gases during the RTA.In Figure 10, (a) representative is at N ₂The oxygen deposition concentration profile of the wafer of making in the compression ring border, (b) representative is at N ₂The oxygen deposition concentration profile of the wafer of making in gas and the Ar compression ring border, (c) representative is at N ₂Gas and H ₂The oxygen deposition concentration profile of the wafer of making in the compression ring border (d) is represented the oxygen deposition concentration profile of the wafer of making, and (e) is represented at H in Ar compression ring border ₂The oxygen deposition concentration profile of the wafer of making in the compression ring border.

For relatively, under same processing condition, all wafers is carried out RTA and subsequent heat treatment.That is, RTA carried out for 10 seconds under 1250 ℃, and as described above like that, subsequent heat treatment is carried out twice under 800 ℃ of about 4 hours and subsequent 1600 ℃ of about conditions of 16 hours.This results are shown in table 5.

Table 5

Gases used	Oxygen deposition substrate concentration (the cm of peak value place ^-3)	Body region oxygen deposition substrate concentration (cm ^-3)	The degree of depth of DZ (μ m)	The COP dissolving power
Gases used			The degree of depth of DZ (μ m)	The COP dissolving power	Ar	8×10 ⁹	8×10 ⁹	50	In
H ₂	6×10 ⁹	6×10 ⁹	60	High	Ar	8×10 ⁹	8×10 ⁹	50	In
H ₂	6×10 ⁹	6×10 ⁹	60	High	N ₂	3×10 ⁹	≈1×10 ⁵(detectability)	0	Do not have
N ₂+Ar	2×10 ¹⁰	5×10 ⁹	10	In	N ₂	3×10 ⁹	≈1×10 ⁵(detectability)	0	Do not have
N ₂+Ar	2×10 ¹⁰	5×10 ⁹	10	In	N ₂+H ₂	1×10 ¹⁰	5×10 ⁹	15	High

Figure 11 shows when the RTA of Fig. 5 implements in Ar compression ring border, near the COP dissolved figure of silicon wafer surface.Usually, have incomplete octahedral voids shape at the COP that forms by CZ technology crystal ingot growing period, and silicon oxide layer 22 is formed on the inboard of hole 22a.In addition, when the RTA process at Ar or H ₂When carrying out in the compression ring border, near the COP that occurs wafer surface is dissolved, and wherein this gas provides gap silicon injection effect to wafer surface.

Describe the dissolution mechanism of COP in detail, when during crystal growth with starting point concentration O _iDuring in conjunction with the cooling of the crystal ingot of oxygen, the oxygen concn in this crystal ingot becomes supersaturation under the refrigerative temperature.Therefore, also supersaturation and surpass the predetermined solubleness (in Figure 11, indicating) of oxygen of the initial oxygen concentration of the wafer that forms by crystal ingot with " S ".Yet, since the oxygen by wafer surface to external diffusion, be equal to or less than predetermined solubleness " S " near the initial oxygen concentration of wafer surface.Simultaneously, in the body region of wafer, oversaturated oxygen is provided for hole 20a and is used for forming silicon oxide layer 22 in the inside of hole 20a.In addition, because (promptly near wafer surface, zone among Figure 11 between surface and the dotted line " T ") initial oxygen concentration is less than the predetermined solubleness " S " of oxygen, so secretion is come out in the silicon oxide layer (not shown) of oxygen from be formed on hole 20b, owing to the gap silicon injection effect of the gas that provides during the RTA process, silicon is arranged on 20b inboard, hole simultaneously.The result is that the size of hole 20b reduces and hole 22b finally disappears.

Because the solubility effect of COP, can be generalized on the various wafers according to the RTA process of the embodiment of the invention.As shown in table 5, this COP solubility effect is by using H ₂Gas is than using Ar gas more can strengthen.

Figure 12 to Figure 16 is presented at after the RTA process through subsequent heat treatment, and has the photo that the oxygen deposition thing of wafer of the oxygen deposition concentration profile of Figure 10 distributes.Particularly, Figure 12 is corresponding to using N ₂The situation of gas, Figure 13 is corresponding to the situation of using Ar gas, and Figure 14 is corresponding to using H ₂The situation of gas, Figure 15 is corresponding to using N ₂The situation of gas and Ar gas, and Figure 16 is corresponding to using N ₂Gas and H ₂The situation of gas.In addition, the end face of the left side shows wafer of each figure, and the bottom surface of its right side shows wafer.

Figure 17 to Figure 21 is the photo that is presented at the degree of depth of the DZ that forms the wafer surface near, and this place's non-oxygen precipitating thing exists, and wafer after RTA handles through subsequent heat treatment and have the oxygen deposition concentration profile of Figure 10.Particularly, Figure 17 represents and uses N ₂The situation of gas, Figure 18 represents the situation of using Ar gas, and Figure 19 represents and uses H ₂The situation of gas, Figure 20 represents and uses N ₂The situation of gas and Ar gas, and Figure 21 represents use N ₂Gas and H ₂The situation of gas.As can from table 5 notice, DZ can only be at N ₂Compression ring forms in the border.

Figure 22 A to Figure 24 B shows primary COP shape, and after the RTA process photo of altered COP shape.Particularly, Figure 22 A and Figure 22 B representative is at N ₂Carry out the situation of RTA in the compression ring border, Figure 23 A and Figure 23 B representative are at N ₂With the situation of carrying out RTA in the Ar compression ring border, and Figure 24 A and Figure 24 B representative are at N ₂And H ₂Carry out the situation of RTA in the compression ring border.As shown in table 5, at N ₂COP does not dissolve basically in the compression ring border.In addition, at N ₂Gas and Ar or H ₂The dissolving of COP is stably in the gas blended gaseous mixture environment, and especially, COP can be at H ₂Dissolving fully in the compression ring border.According to this result, also can derive, fully dissolve COP in the RTA process that can promote of the reduction of primary COP size at Fig. 5.

Embodiments of the invention can be by the RTA process to silicon wafer execution graph 5, and the oxygen deposition thing that control forms via the subsequent heat treatment circulation of carrying out in the semiconductor device manufacturing usually distributes.The embodiment of the embodiment of the entire wafer preparation in the RTA process implementation process according to the present invention and the wafer preparation that works when using RTA will be described now.

Figure 25 is the wafer preparation schema that shows according to the embodiment of the invention, particularly, has shown crystal growth (S10) conventional wafer process technology afterwards.The general introduction of conventional Wafer Machining be disclosed in S.Wolf and R.N.Tanber in the textbooks of 1986 works " the silicon processing in super large-scale integration epoch; volume 1; processing technology (Silicon Processing for the VLSI ERA; Volume 1; ProcessTechnology) " 1 to 35 page of chapter 1, its disclosure thereby be incorporated herein by reference.With reference to Figure 25, conventional wafer process technology comprise use CZ lift device growth crystal ingot crystal growth step (S10), with crystal ingot be cut into wafer slicing step (S12), make each slicing edge become the etch step (S14) of circle or etching slice surface.Then, at first cleaning (S16) that cleans slice surface afterwards, carry out the alms giver and remove step (S18), polishing forms the wafer top surface (S20) of semiconductor device, the wafer of cleaning polishing in second cleaning (S22).Encapsulate the wafer (S24) of gained then.

Remove in the step (S18) the alms giver according to the RTA of Fig. 5 of the embodiment of the invention and to carry out.RTA according to other embodiments of the present invention can carry out in independent step.But from the viewpoint of cost, preferably RTA removes in the step (S18) the alms giver and carries out.Usually, the alms giver removes and refers to, the oxygen composition that has and serve as the electron donor of implanting impurity ion in the silicon ingot, during follow-up semiconductor device manufacturing with ionic species will be included in, be transformed into the oxygen deposition thing via the thermal treatment in the wafer process technology, to reduce the possibility that works as the alms giver.This thermal treatment was carried out about 30 seconds or longer at about 700 ℃ in the RTA stove.

Figure 27 is the sketch that traditional C Z lifts device, and crystal growth (S10) is carried out therein.As shown in figure 27, CZ lifts device 100 and comprises a smelting furnace, a drawing machine for quartz structure, an environmental control and a computer control system.The CZ stove is commonly referred to as the hot-zone smelting furnace.This hot-zone smelting furnace comprises crucible 106, a turning axle 110 that can be pivoted by the lower support (succeptor) 108 and the first direction 112 shown in the edge of graphite manufacturing that adds hot device 104, one an available quartzy manufacturing.

Cooling jacket or mouth 132 are by the exterior cooling device cooling such as water-cooled.Thermoscreen 114 can provide additional heat distribution.Heat jar (a heat pack) 102 fills up heat-sink material 116 so that additional heat distribution to be provided.

The drawing machine for quartz structure comprises crystal lifting rod 120, and it can pivot along as directed and first direction 112 opposite second directions 122.Crystal lifting rod 120 comprises that one is positioned at the seed holder 120a of its end.Seed holder 120a clamping seed crystal 124, it is by pulling out in the molten silicon in the crucible 106 126 to form crystal ingot 128.

Environmental control system can comprise chamber big envelope 130, cooling jacket 132 and other unshowned gas flow controller and vacuum evacuating system.Computer control system can be used to control heating unit, lift device and other electronics and mechanical organ.

For the growing single-crystal silicon ingot, seed crystal 124 contact molten silicons 126, and (make progress) gradually vertically and pull out.Molten silicon 126 cooling and be solidified into 131 places, interface that silicon single crystal occurs in crystal ingot 128 and molten silicon 126.As shown in figure 27, interface 131 is with respect to molten silicon 126 concaves.

Controlled oxygen deposition concentration profile as shown in Figure 4 can obtain from least three types silicon wafer by RTA embodiment according to the present invention.Especially, can be applied to not exist such as the gap according to the RTA of the embodiment of the invention and assemble and " perfection " wafer of point defect such as accumulation of vacancies; Accumulation of vacancies only occurs in the rich room district in a predetermined radii of center wafer, and does not have accumulation of vacancies and gap accumulative " half is perfect " wafer outside the district of rich room; And in entire wafer, only comprise accumulation of vacancies, and accumulative wafer very close to each other.But the present invention is not limited to above-mentioned wafer, and comprises the adaptable all types wafer of principle of the present invention.As mentioned above, embodiments of the invention are orientated controlled oxygen deposition concentration profile as shown in Figure 4, and RTA process that this distribution can be by execution graph 5 and the subsequent heat treatment that can use silicon wafer of the present invention obtain.In addition, for COP, the embodiment of the invention provides wherein that COP only appears in the body region of wafer, and does not appear at the wafer among the DZ.

In order to prevent the defective of silicon wafer, the crystal growing process of high purity crystal ingot is paid close attention in a lot of applied researcies.For example, well-known, the rate of pulling and the thermograde in the hot zone structure of seed crystal should Be Controlled.The control of the thermograde (G) at the crystal ingot rate of pulling (V) and crystal ingot-molten silicon interface by be described in detail in fertile you husband of section (Voronkov) be published in " crystal growth journal (Journal of Crystal Growth) " nineteen eighty-two the 59th 625 to 643 pages of volumes " spiral shell type defective forms mechanism (The Mechanism of SwirlDefects Formation in Silicon) in the silicon " in.In addition, the application of fertile your husband of section theory can wait inventor and be published in the title delivered during on November 25th to 29,1996 " second international symposium of advanced silicon materials science and technology (Proceedings of the Second International Symposium on AdvancedScience and Technology of Silicon Material) " and find in 519 pages of the article of " lattice defect is to the influence (Effect of Crystal Defects on Device Characteristics) of equipment energy characteristic ".This article discloses as V the ratio of G (be called V/G than) subcritical than (V/G) ^*The time, rich interstitial area forms, and is higher than critical ratio (V/G) and work as the V/G ratio ^*The time, rich room district forms.

Particularly, Figure 26 be show corresponding point defect distribution and V/G in the silicon ingot than between the synoptic diagram of relation.As shown in figure 26, at the crystal ingot growing period, to being higher than critical V/G than (V/G) ^*The V/G ratio, rich room district forms.Equally, to vacancy concentration greater than critical vacancy concentration C _v ^*The V/G ratio, accumulation of vacancies forms, and to gap concentration greater than the critical gap concentration C _I ^*The V/G ratio, the gap assemble to form.In addition, in Figure 26, from (V/G) _I ^*To (V/G) _B ^*Width represent B-band, it is the gap of relative defective (small size dislocation), and from (V/G) _V ^*To (V/G) _P ^*Width represent P-band, it is an O.S.F. annular (a large size oxygen deposition thing).

Embodiments of the invention can be applied to not have defective the crystal ingot growing period have the V/G ratio between B-band and P-band perfect wafer, have half perfect wafer of the V/G ratio that comprises the P-band, and owing to be higher than corresponding to critical vacancy concentration C _v ^*Critical V/G than (V/G) ^*V/G and in entire wafer, form the wafer of accumulation of vacancies.

Can be applicable to perfect wafer of the present invention and partly obtained detailed description in application, the U.S. Patent application the 09/320th, 210 and the 09/320th, 102 with half perfect wafer at U.S. Patent application the 08/989th, 591 and continuation thereof, these applications are referred to herein.Thereby its detailed description will be omitted.

Figure 28 is the sketch that disclosed improved CZ lifts device in continuing the part application, and thermoscreen 214 wherein and CZ shown in Figure 27 lift device and compare and improve.Briefly, as shown in figure 28, improved CZ lifts device 200 and comprises a smelting furnace, a drawing machine for quartz structure, an environmental control and a computer control system.The hot-zone smelting furnace comprises the turning axle 210 that first direction 212 pivots shown in a well heater 204, a crucible 206, a lower support 208 and the edge.Cooling jacket 232 and thermoscreen 214 can provide additional heat distribution, and heat jar 202 comprises thermal absorption material 216 so that additional heat distribution to be provided.

The drawing machine for quartz structure comprises crystal lifting rod 220, this bar can along shown in the second direction 222 opposite with first direction 212 sway.Crystal lifting rod 220 comprises that one is positioned at the seed holder 220a of its end.Seed holder 220a clamping seed crystal 224, it is by pulling out in the molten silicon in the crucible 206 to form crystal ingot 228.

Environmental control system can comprise chamber big envelope 230, cooling jacket 232 and other unshowned gas flow controller and vacuum evacuating system.Computer control system can be used for controlling heating unit, lifts device and other electronics and mechanical organ.

For growing single-crystal body silicon ingot, seed crystal 224 contacts with molten silicon 226 and (makes progress) gradually vertically and lifts.Molten silicon 226 cooling also is cured as silicon single crystal and occurs in 231 places, interface between crystal ingot 228 and the molten silicon 226.Lift device with the CZ of Figure 27 and compare, the CZ of Figure 28 lifts device 200 and further comprises insulation plate 234 in the thermoscreen 214, and it is allowed and controls the V/G ratio more accurately.

Figure 29 is the sketch that lifts device according to the improved CZ of the embodiment of the invention, and Figure 30 shows that in detail the CZ of Figure 29 lifts the improvement part of device.In Figure 29 and Figure 30, be used to represent components identical with the used identical Reference numeral of Figure 28, and the difference of having only CZ with Figure 28 to lift device will be described.Shown in Figure 29 and 30, the variation that is lifted device by the CZ of Figure 28 comprises the shape of insulation plate 300 and the additional installation of thermal baffle 360.Similar annular have 90 ° of rotation trapezoid insulation plates 300 comprise be preferably vertical in insulation plate wall 310 and outer insulation plate wall 330, and in connecting and the insulation plate of outer

insulation plate wall

310 and 330 push up 340 and insulation plate at the bottom of 320.Herein, insulation plate top 340 is inclined upwardly to become the angle at β angle with level to outer insulation plate wall 330 by interior insulation plate wall 310, simultaneously at the bottom of the insulation plate 320 from interior insulation plate wall 310 to outer insulation plate wall 330 becoming the angle at α angle downward-sloping with level, trapezoidal shown in the formation.

Annular insulation plate 300 can be filled with the heat-sink material (not shown), and can be made by ferrous acid carbon (carbon ferrite).

In addition, insulation plate 300 is fixed on the top of heat jar 202 by support component 350.Thermal baffle 360 is installed between the insulation plate top 340 and cooling jacket 232 of insulation plate 300, around the crystal ingot that is drawn out.

The structure that Figure 29 and CZ shown in Figure 30 lift device can allow the rate of cooling of crystal ingot to improve.Be present in the square root that in general hole size in the crystal ingot of pulling out is proportional to crystal ingot-molten silicon initial vacancy concentration at the interface, be inversely proportional to the square root of crystal ingot rate of cooling.As described in reference Figure 11, if during crystal growth, form be present in hole size in the crystal ingot less than predetermined size, though the crystal ingot of pulling out comprises the hole, these holes can be dissolved from DZ by the RTA process according to the embodiment of the invention.

Therefore, in order to reduce the size in hole in the crystal ingot, this is desirable according to embodiments of the invention, and the rate of cooling of crystal ingot can improve.When the rate of cooling of crystal ingot improved, the thermograde Gc at crystal ingot center may increase.Therefore, constant if V/G is compared to predetermined defect distribution, then crystal ingot pulls out speed (V) and should increase.

According to embodiments of the invention, temperature based on the crystal ingot center, for the rate of cooling with crystal ingot be increased at least 1.4 ° of K/min or more than, so that crystal ingot is cooled to the preset temperature of crystal ingot from crystal ingot-molten silicon temperature at the interface, the length a of interior insulation plate wall 310, the length c of outer insulation plate wall 330, the angle beta on insulation plate top 340,320 angle [alpha] at the bottom of the insulation plate, crystal ingot 228 between the interior insulation plate wall 310 apart from d, crucible 206 to outer insulation plate wall 330 apart from f, between the thermal

insulation cover wall

310 and 330 apart from e, interior insulation plate wall 310 is to the distance b between the molten silicon 226, and in the position of thermal baffle 360 at least one can change.

CZ in Figure 29 lifts in the device, because the high rate of cooling of the crystal ingot of pulling out, and the pulling out speed and can improve of crystal ingot, for example, in 0.50 to 1.00mm/min scope, thereby the productivity of crystal ingot can improve.In addition, the process redundancy that lifts the perfect wafer of device manufacturing or half perfect wafer by CZ shown in Figure 28 can offer the growth of crystal ingot.

In drawing and description, the typical preferred embodiment of the present invention is disclosed, although used certain conditions, they only are in order to explain and illustrative purposes, rather than limitation of the present invention, the field of the invention limits in claims.

Claims

One kind have end face, bottom surface and between end face and bottom surface the silicon wafer of the oxygen deposition concentration profile in it, the oxygen deposition concentration profile comprises:

Lay respectively at from the end face of wafer and first and second peak values at the first and second predetermined depth places, bottom surface;

Between the end face of wafer and first peak value and the bottom surface of wafer and the stripping section between second peak value; And

Concave region between first and second peak values.
2. silicon wafer as claimed in claim 1, wherein, the oxygen deposition concentration profile is centrally placed in the silicon wafer median plane symmetry between end face and bottom surface relatively.
3. silicon wafer as claimed in claim 1, wherein, the degree of depth of stripping section from the end face of silicon wafer and bottom surface 10 μ m in 40 mu m ranges.
4. silicon wafer as claimed in claim 3, wherein, the degree of depth of stripping section is apart from the top 30 μ m on two surfaces of silicon wafer.
5. silicon wafer as claimed in claim 1, wherein, the oxygen deposition substrate concentration at the first and second peak value places is at least 1 * 10 ⁹Cm ^-3
6. silicon wafer as claimed in claim 1, wherein, the oxygen deposition substrate concentration in the concave region between first and second peak values is at least 1 * 10 ⁸Cm ^-3
7. silicon wafer as claimed in claim 1, wherein, the primary precipitation thing of crystal only exists only in the concave region between first and second peak values of wafer.
One kind have end face, bottom surface and between end face and bottom surface the silicon wafer of the vacancy concentration in it, vacancy concentration comprises:

Lay respectively at first and second peak values from the first and second predetermined depth places of the end face of wafer and bottom surface;

Zone with predetermined vacancy concentration, this concentration subcritical concentration, this zone is between the end face of wafer and first peak value and between the bottom surface and second peak value of wafer; And

Concave region between first and second peak values.
9. silicon wafer as claimed in claim 8, wherein, vacancy concentration is centrally placed in the silicon wafer median plane symmetry between end face and bottom surface relatively.
10. silicon wafer as claimed in claim 8, wherein, the primary precipitation thing of crystal only exists only in the body region between first and second peak values of wafer.
11. a method of making silicon wafer comprises:

On end face that is included in wafer and bottom surface, have in the gaseous mixture environment of the gas of room injection effect and gas with gap injection effect, silicon wafer is implemented rapid thermal annealing, to generate the nucleating center, oxygen deposition thing growth position is served as in this nucleating center in subsequent heat treatment, in the nucleating center concentration distribution from the wafer top surface to the bottom surface, the nucleating center concentration distribution comprises:

Lay respectively at first and second peak values from the first and second predetermined depth places of the end face of wafer and bottom surface;

Zone with predetermined forming core centre concentration, the concentration subcritical concentration of this nucleating center, this zone is between the end face of wafer and first peak value and between the bottom surface and second peak value of wafer; And

Concave region between first and second peak values.
12. method as claimed in claim 11, wherein, the step of carrying out rapid thermal annealing process also produces the vacancy concentration from the wafer top surface to the bottom surface, and this vacancy concentration comprises:

Lay respectively at first and second peak values from the first and second predetermined depth places of the end face of wafer and bottom surface;

Zone with predetermined vacancy concentration, this concentration subcritical concentration, this zone is between the end face of wafer and first peak value and between the bottom surface and second peak value of wafer; And

Concave region between first and second peak values.
13. method as claimed in claim 11 also is included in and carries out subsequent heat treatment on the silicon wafer to form the step of the oxygen deposition concentration profile from the wafer top surface to the bottom surface, this oxygen deposition concentration profile comprises:

Lay respectively at first and second peak values from the first and second predetermined depth places of the end face of wafer and bottom surface;

Between the end face of wafer and first peak value and the bottom surface of wafer and the stripping section between second peak value; And

Concave region between first and second peak values.
14. method as claimed in claim 11, wherein, gaseous mixture comprises nitrogen and argon gas.
15. method as claimed in claim 12, wherein, gaseous mixture comprises nitrogen and argon gas.
16. method as claimed in claim 13, wherein, the oxygen deposition substrate concentration in first and second peak values and concave region can recently be controlled by the mixing of adjustments of gas mixture.
17. method as claimed in claim 11, wherein, the degree of depth with zone of predetermined forming core centre concentration can recently be controlled by the mixing of adjustments of gas mixture.
18. method as claimed in claim 16, wherein, the oxygen deposition substrate concentration in first and second peak values and concave region also can be controlled by the temperature and time of regulating rapid thermal annealing process.
19. method as claimed in claim 17, wherein, the degree of depth with zone of predetermined forming core centre concentration also can be controlled by the temperature and time of regulating rapid thermal annealing process.
20. method as claimed in claim 11, wherein, the step of carrying out rapid thermal anneal process comprises with the speed of at least 30 ℃/Sec cools off wafer fast.
21. method as claimed in claim 20 wherein, is carried out the step of rapid thermal anneal process and is carried out under at least 1150 ℃ temperature.
22. method as claimed in claim 21, wherein, the step of carrying out rapid thermal anneal process is carried out for some time of at least 5 seconds.
23. method as claimed in claim 21, wherein, the step of carrying out rapid thermal anneal process was carried out 30 seconds or the longer time under 1150 ℃ or higher temperature.
24. method as claimed in claim 21, wherein, the step of carrying out rapid thermal anneal process is carried out 5 seconds time under 1250 ℃ or higher temperature.
25. method as claimed in claim 13, wherein, the step that silicon wafer is carried out subsequent heat treatment is carried out 4 to 20 hours time under the temperature between 800 ℃ and 1000 ℃.
26. method as claimed in claim 13, wherein, the oxygen deposition concentration profile is controlled as the silicon wafer median plane symmetry that is centrally placed in relatively between end face and bottom surface.
27. method as claimed in claim 11, wherein, have predetermined forming core centre concentration the zone the degree of depth from the end face of silicon wafer and bottom surface 10 μ m in the scope of 40 μ m.
28. method as claimed in claim 11, wherein, the degree of depth with zone of predetermined forming core centre concentration is end face and bottom surface 30 μ m from silicon wafer.
29. method as claimed in claim 13, wherein, the oxygen deposition substrate concentration at the first and second peak value places is at least 1 * 10 ⁹Cm ^-3
30. method as claimed in claim 13, wherein, the oxygen deposition substrate concentration in the concave region between first and second peak values is at least 1 * 10 ⁸Cm ^-3
31. method as claimed in claim 11, wherein, rapid thermal annealing is removed in the step the alms giver of the wafer process of silicon wafer and is carried out.
32. method as claimed in claim 11 also is included in and carries out the rapid thermal anneal process end face of polished wafer afterwards.
33. method as claimed in claim 11 wherein, is carried out before the described step of carrying out:

Distribute and to pull out in the molten silicon of crystal ingot from the smelting furnace of hot-zone according to the crystal ingot rate of pulling, wherein crystal ingot to pull out speed enough high preventing that the gap accumulative from forming, but want enough low so that the formation of accumulation of vacancies is limited in the district of axial rich room, crystal ingot center; And

Crystal ingot is radially cut into slices so that silicon wafer to be provided.
34. method as claimed in claim 11 wherein, is carried out before the described step of carrying out:

Distribute according to a crystal ingot rate of pulling, to pull out in the molten silicon of crystal ingot from the smelting furnace of hot-zone, the rate distribution of pulling out of described crystal ingot produces the rich room district that comprises accumulation of vacancies at the center of crystal ingot, and the pure district beyond the district of rich room, pure zone comprises no accumulation of vacancies and accumulative gap, gap point defect; And

Crystal ingot is radially cut into slices so that silicon wafer to be provided.
35. method as claimed in claim 11 wherein, is carried out before the described step of carrying out:

Distribute according to the crystal ingot rate of pulling, will pull out in the molten silicon of crystal ingot from the smelting furnace of hot-zone, described crystal ingot to pull out speed enough high preventing gap accumulative formation, but to enough hang down to prevent the formation of accumulation of vacancies; And

Crystal ingot is radially cut into slices so that silicon wafer to be provided.
36. method as claimed in claim 11 wherein, is carried out before the described step of carrying out:

Distribute according to the crystal ingot rate of pulling, will pull out in the molten silicon of crystal ingot from the smelting furnace of hot-zone, the rate distribution of pulling out of described crystal ingot produces point defect, does not assemble and accumulation of vacancies and do not produce the gap; And

Crystal ingot is radially cut into slices so that silicon wafer to be provided.
37. method as claimed in claim 11 wherein, is carried out before the described step of carrying out:

Distribute according to the crystal ingot rate of pulling, will pull out in the molten silicon of crystal ingot from the smelting furnace of hot-zone, wherein crystal ingot to pull out speed enough high, thereby accumulation of vacancies forms in the whole diameter range of crystal ingot, assembles and do not form the gap; And

Crystal ingot is radially cut into slices so that silicon wafer to be provided.
38. method as claimed in claim 33, wherein, the accumulation of vacancies that is formed in lifting step in the silicon wafer is of a size of 0.2 μ m.
39. as the method for claim 34, wherein, the accumulation of vacancies that is formed in lifting step in the silicon wafer is of a size of 0.2 μ m.
40. as the method for claim 35, wherein, the accumulation of vacancies that is formed in lifting step in the silicon wafer is of a size of 0.2 μ m.
41. method as claimed in claim 33, wherein, crystal ingot lifts step and also comprises, based on center crystal ingot temperature, with the rate of cooling of at least 1.4 ° of K/min the crystal ingot of pulling out is cooled to preset temperature.
42. method as claimed in claim 34, wherein, crystal ingot lifts step and also comprises, based on center crystal ingot temperature, with the rate of cooling of at least 1.4 ° of K/min the crystal ingot of pulling out is cooled to preset temperature.
43. method as claimed in claim 35, wherein, crystal ingot lifts step and also comprises, based on center crystal ingot temperature, with the rate of cooling of at least 1.4 ° of K/min the crystal ingot of pulling out is cooled to preset temperature.
44. method as claimed in claim 33, wherein, crystal ingot lifts step and comprises, with the rate of pulling in 0.5 to 1.0mm/min scope crystal ingot is pulled out.
45. method as claimed in claim 34, wherein, crystal ingot lifts step and comprises, with the rate of pulling in 0.5 to 1.0mm/min scope crystal ingot is pulled out.
46. method as claimed in claim 35, wherein, crystal ingot lifts step and comprises, with the rate of pulling in 0.5 to 1.0mm/min scope crystal ingot is pulled out.