MXPA96004103A - An entraming demapeator of a decoder - Google Patents

Abstract

The present invention relates to a convolutional decoder (200, FIGS. 2 and 3) of a plurality of pragmatic framework codes, each of which is defined by a plurality of convolutionally encoded symbol packets, applied as digital input signals in phase (I) and in quadrature phase (Q) thereto, wherein said pragmatic framework codes comprise a different code for each series of symbols constellation in the I, Q plane that includes an even power of two of the number of symbols arranged in a bit-by-symbol, square grid mapping, including the maximum constellations of said square grid symbol constellations 22Y symbols, where y is a first positive integer that has a given value of at least 2; the convolutional decoder includes a framework demapping (310) to demap each of the plurality of pragmatic framework codes; because (1) the bit-to-symbol mapping of the square grid of each series of constellation is such that the alternative cells of the odd rows of the square grid define a first sub-series of symbols; the remaining cells of the odd rows of the square grid defines a second sub-series of symbols, the alternative cells of the even rows of said square grid define a third sub-series of symbols, and the remaining cells of the even rows of the square grid define a fourth sub-series of symbols, and (2) the frame demapping device is characterized by: a channel I random access memory (RAM 400) having an effective depth of locations of 2 (x + 2) storage locations, where x is one second positive integer that has a given value, greater than the first positive integer, each storage location has an effective amplitude at least sufficient to store an annotation of a look-up table that defines I, and having y-bits: a channel Q RAM (402) having an effective depth of 2 (x + 2) storage locations, each storage location having an effective width at least sufficient to store an annotation of a table query defining Q, which has y-bits, first means (312) to apply a first x-bit input to said channel I RAM to define the value of said digital input signal in phase (I) and to apply a second x-bit input to the Q-channel RAM to define the value of the quadrature digital input signal (Q); second means (308) to apply a 2-bit input to both the I channel RAM and the Q channel RAM to define a selected sub-series of said four sub-series, according to the binary value of the 2-bit input applied, third means (204, figures 2 and 3), to preload the query table of the channel I RAM, according to a selected series of such symbol series s of constellation, in such a way that the bit mapping of component I of that symbol of the selected sub-series of said four sub-series of the selected series of constellation series that is closer in value to the value defined by the signal digital input in phase (I) to channel I RAM, read as the channel I RAM output; fourth means (204) to preload the Q channel RAM look-up table according to a selected series of said series of constellation symbols, in such a way that the bit mapping of the Q component of that symbol of the selected sub-series of the four sub-series of the selected series of the constellation series that is closest in value to the value defined by the quadrature digital input signal (Q) to the Q channel RAM being read, at the output of said channel RAM

Description

"A TAMPER DESMAPEATOR OF A CONVOLUTIONAL DECODER" This invention relates to a digital processor apparatus, suitable for use in a multi-channel receiver of compressed digital television data, corrected for positive error (FEC), an acronym of its English designation For ard-Error-Corrected, transmitted by satellite, terrestrial and cable antenna and, more particularly, a framework for a convolutional decoder based on a Viterbi algorithm, capable of decoding pragmatic framework codes. It is known in the art to use positive error correction that includes convolutional coding in the transmission of digital data encoded by a noisy channel, from a transmitter to a receiver, which includes a branched metric computer for a convolutional decoder that is based on the Viterbi algorithm. The Viterbi algorithm is very commonly used to decode a coded convolutional bit sequence transmitted by a noisy channel. At the heart of the Viterbi algorithm there is a series of repetitive operations of add-compare-select, which accepts as input certain metrics (called branched metrics), computed in each symbol received from the demodulator. For satellite, cable or terrestrial transmission of high data rate signals, these computations need to be made at very high speeds. Additionally, in a modem-decoder that operates on different channels with different (but related) coding schemes, the cost of computing the branch metrics becomes excessive in terms of a • consultable table or real peripherals to perform these computations. In the case of a satellite transmission channel, it is customary to transmit a quaternary phase shift code (QPSK) code, acronym for its perforated English designation Quaternary Phase Shift Keyed, which is known as the convolutional receiver decoder. In the case of a terrestrial or cable transmission channel, a particular pragmatic lattice code (such as a quadrature amplitude modulation code (QAM, acronym for its English designation Quadrature Amplitude Modulation), modulation in amplitude is used. of phase (PAM, acronym for its designation in English Phase Amplitude Modulation), or code with a key based on the phase shift (PSK, acronym for its designation in English Phase Shift Keyed), known for the convolutional receiver decoder. , the prior art discloses the use of a pragmatic framework code as a code for practical QAM transmission of high definition television (HDTV, acronym for its designation in English High Definition Television.) Reference is made to US Patent No. 5,497,401 , titled "A Branch Metric Computer for a Viterbi Decoder of a PuncLured and Pragmatic Trellis Code Convolutional Decoder Suita Use for a Multi-channel Receiver of Satellite, Terrestrial and Cable Transmitted FEC Compressed-Digital Television Data "(" A Metric Branch Computer for a Viterbi Decoder of a Convolutional Decoder of Perforated and Pragmatic Lattice Code, Suitable for Use in a Receiver of Multiple Channels of Digital Television Data Compressed, FEC, Transmitted by Satellite, Terrestrial and Cable "). In the past, the convolutional decoder based on the Viterbi algorithm was typically designed to operate with only a predetermined type of convolutional code. However, multi-channel digital television receivers are likely to enter the mass-produced market in the near future and, in a short time, replace the currently used analog television receivers. Satellite transmission, direct broadcast to television receivers is now available in addition to terrestrial and cable transmission to them. Thus, it is convenient that the convolutional decoders of the digital television receivers of multiple channels respond selectively to the type of code (either of perforated or pragmatic framework, as the case may be) and the type of modulation (PSK, including both QPSK and 8- PSK, PAM or QAM, depending on the case) of the channel that is being received by the multi-channel digital television receiver. Additionally, mass-produced television receivers must be designed taking into account the reduction in cost and complexity. The aforementioned U.S. Patent No. 5,497,401 is directed to a structure for the metric branching computer for the Viterbi decoder of the convolutional decoder, which can be incorporated into said multi-channel television receiver, which is designed taking into account the reduction in the cost and complexity. First, the branching metric computer structure employs a RAM memory (random access memory) pre-loaded during an initialization phase with programmable I and Q query tables, previously computed, coming from a microcontroller interface applied as a control input thereto. Secondly, this branching metric computer structure computes a one-dimensional measure of the distance between two points in the two-dimensional plane I, Q, substituting the sum of the I and Q components (I + Q) of the distance between the two points (the so-called "Manhattan" distance), for the Euclidean distance between the two points (I2 + Q2). This allows the I and Q components to be handled independently of one another, thereby reducing both the cost and the complexity of the branch metric computer. The convolutional decoder described in the aforementioned US patent, under the control of the microcontroller interface, may be operated alternately, either in the particular punched code mode (neither of which uses a lattice demapper) or a certain code mode. particular pragmatic lattice (all of which use a lattice demayer). The present invention is directed both to the demapping techniques and to the structure of a framework demayer for the type of convolutional decoder described in the aforementioned US Patent No. 5,497,401, when operating in a pragmatic framework code mode (such as for codes 16, 32, 64, 128 and 256 QAM and for an 8-PSK code, by way of examples). This framework demapper, which is designed with cost and complexity reduction in mind, provides minimal storage requirements compared to a framework code demayer that uses ROM memory storage. (read only memory) for the QAM framework codes. More specifically, the present invention is directed to said demapping device for a plurality of codes comprising a different code for each of a series of symbols constellations in the I, Q plane that includes: (1) an even power of 2 numbers of symbols arranged in a bit-by-symbol mapping, square grid; (2) an odd power of two symbol numbers arranged in bit mapping to transverse grid symbol and / or (3) a code 8-PSK. The respective channel I and Q channel RAM memories, each of which includes a look-up table that is selectively programmed for each of the QAM codes, are employed in both categories (1) and (2). In the case of category (1), the respective outputs of the I channel and Q channel RAM memories are directly advanced as the output of the framing demayer. In the case of category (2), the respective outputs of the channel I and Q channel RAM memories are applied as inputs to a remaper RAM, and the output of the remaper RAM memory is sent as the output of the frame demapping. In the case of category (3), an 8-PSK demapping logic means is used to demap the 8-PSK code and the output of the demapping logic means is output as the framing demapping output. In those cases in which the framework demapper responds to two or all three categories (1), (2) and (3), a MUX selector is used to send the output of one of the selected categories as the output of the demapping framework.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates the different types of transmission channels that are received by a compressed, multi-channel digital television receiver, transmitted from a compressed digital television transmitter, corrected in sending or positive error; Figure 2 is a block diagram showing the relationship between the convolutional decoder, the demodulator that applies an input to the decoder and a microcontroller interface to the decoder of the multi-channel digital television receiver, of Figure 1; Figure 3 is a block diagram of the structural elements of the convolutional decoder shown in Figure 2, when programmed by the microcontroller interface to operate in a pragmatic framework code decoder mode showing the interface coupling of the microcontroller of Figure 2 shows the structural elements of the convolutional decoder; Figure 4 is a block diagram of the structural elements of the framing demayer shown in Figure 3; and Figure 5 illustrates the bit-to-symbol mapping for 8-PSK coded in framework (R = 2/3 coded rate). As shown in FIG. 1, the multichannel compressed digital television receiver 100 is capable of selectively receiving digitally encoded television data, transmitted on each of a plurality of different channels. That plurality of channels include the satellite transmission channel that transmits digitally encoded television data from a corrected television transmitter 104 for sending error; the terrestrial transmission channel 106 that transmits digitally encoded television data from a television transmitter 108 corrected for sending error; and the cable television channel 110 that transmits digitally encoded television data from a corrected television transmitter 112 in sending error. As shown in the art, the send error correction in the transmitter typically comprises convolutionally encoding the successively transmitted symbol packets of compressed digital television data, already encoded. As is further known in the art, while punctuated codes based on QSPK are typically employed, for the transmission of convolutional encoded data over a satellite channel, potentially higher-pragmatic pseudo-frame codes could be employed (ie, 8, 16 , 32, 64, 128 and 156) n / n + 1, for transmission based on PAM, PSK or QAM of encoded data convolved, by terrestrial or cable channels. Therefore, the multi-channel receiver 100 is required to incorporate a convolutional decoder that is capable of decoding any of the pragmatic lattice codes n / n + 1 of upper alphabet, which are based on PAM, PSK or QAM, or perforated with base in QSPK, depending on the channel selected among the multiple channels that are received. More specifically, the multi-channel receiver 100 comprises a digital processor apparatus which, as shown in Figure 2, includes the convolutional decoder 200 of the receiver and the receiver demodulator 202 which, as is known in the art, applies each of a plurality of convolutionally encoded symbol packets. , received successively, as the signal input data to the convolutional decoder 200 of the receiver. Each packet of successively received symbols, which contains this data, defines a point in the in-phase plane (I), quadrature phase (Q). The digital processor apparatus of the multichannel receiver 100 further comprises a microcontroller that includes a microcontroller interface 204 for applying a control input to the convolutional decoder 200 of the receiver. The microcontroller interface 204 provides a list of specifications for the convolutional decoder 200 which, among other things, is capable of configuring the operation of the convolutional decoder 200, either as a decoder for punched codes or, alternatively, as a decoder for codes of framework. Figure 3 shows the convolutional decoder 200 configured to operate as a decoder for framing codes. As shown in Figure 3, the structural elements of the convolutional decoder 200 of the receiver include the synchronization circuits 300, the branch metering computer 304, the Viterbi decoder 306, the convolutional encoder 308, the frame demapping 310, the logic delay 312, the synchronization monitor 314 and the selecting means 316. The output data from the demodulator 202 is applied as the input data I, Q to the synchronization circuit 300. For illustrative purposes it is assumed that each of the I and Q data is defined by 6 bits (ie, the input data is applied on a total of 12 parallel input conductors). This allows each of the 64x64 = 4096 different points in the I, Q plane to be defined by the 6 bits I and the 6 bits Q components of the 12 bit input data. The synchronization circuit 300 also receives clock and clock enable inputs (Clk Enb) for it. In addition, the synchronization circuit 300 receives both the control data from the microcontroller interface 204, and supplies it with data, and is directly coupled to the synchronization monitor 314. Each of the elements 302, 304, 306, 308 and 310 it has control data applied to it from the microcontroller interface 204. Furthermore, although not shown in Figure 3, the clock is applied to these elements. The properly synchronized I and Q data are sent from the synchronization circuit 300 to the branch metering computer 304, in response to the data output clock (DOCE) enablement. Additionally, the appropriately synchronized I and Q data are sent through the delay logic 312 to the frame demapping 310 and to the synchronization monitor 314. The metering ram 306 (the details of which form the material of the aforementioned US patent. No. 5,497,401, - derives four separate 5-bit outputs, in response to each of the successively received symbol packets.These four separate 5-bit outputs and the TWELTE signal, from the 304 branch-branching computer, are applied as inputs to the Viterbi decoder 306. The Viterbi decoder 306, which is a rate R = l / 2, restricts the decoder length k = 7, performs the Viterbi algorithm for the frame codes, wherein the metric inputs of the decoder bits, from the 306 branching metric computer, are used to update the states and to make bit decisions. r Viterbi 306 uses means of addition-comparison-selection (ACS, acronym for its name in English add-compare-select), trajectory metric storage means and memory for the surviving trajectories at each framing level. In addition, the Viterbi 306 decoder is also in charge of the metric renormalizations to avoid an accumulation and an excess of the accumulated metrics. A 1-bit output of the Viterbi decoder 306 is applied as an input to the convolutional encoder 308. For the frame codes, the convolutional encoder 308 serves to regenerate the best estimates of the 2 transmitted bits of the code embedded in the 1/2 mode. The output from the encoder 308 is also applied to the synchronization monitor 314. In addition, the 1-bit output of the Viterbi encoder 306 is applied as an input to the selection means 316. The 2-bit output of the convolutional encoder 308 is applied to the framework demapping 310, which is responsible for making symbol decisions. More specifically, the frame demapper 310 uses the 2-bit output from the convolutional encoder 308 for the sub-series selection together with the received I and Q symbol data delayed, which was sent to it by the delay logic 312 (in a way that will be described in detail later) to make those symbol decisions. A 6-bit output from the frame demapping 310 is applied as an input to both the synchronization monitor 314 and the selection means 316. The delay logic 312 counts the delay introduced by the Viterbi decoder 306 / encoder 308 and the associated circuits, and synchronizes the data stream at the output of the encoder 308 with the received symbol stream. The synchronization monitor 314, which is coupled to the synchronization circuit 300, the output of the frame demapping 310, the encoder 308, the delay logic output 312 and the microcontroller interface 204, use the derivation metric information together with a specifying the observation interval from the microcontroller interface 204 to decide the synchronization state. It also gives information to the synchronization circuit 300 for optional automatic synchronization. In an automatic synchronization operation mode, the internal synchronization circuit is used to effect the synchronization function. Alternatively, synchronization could be performed from an external circuit. The synchronization monitor 314 is also used to provide a signal for the demodulator in order to resolve phase ambiguities. This signal is used solely for the purpose of taking into account the phase ambiguities in the demodulator 202 of the receiver. In addition, the synchronization monitor 314. supplies a demodulated synchronization signal to be used by the components located downstream in the receiver 100. The selection means 316, which receives the 1-bit output of the Viterbi decoder 306 and the output of 6 bits of the framework demapping 310, applied as inputs, to them, send these 7 bits in their entirety to their output. These output data, together with a clock signal and a DOCE signal are supplied from the selection means 316 to be used by the components located downstream in the receiver 100. In accordance with the principles of the present invention, a block diagram of a mode of the framework demapping 310 that gives a minimum configuration of peripheral capable of efficiently demapping each of the codes received, delayed in the 3 / 4-16 QAM, regime 4 / 5-32 QAM, regime 5 / 6-64 QAM, regime 6 / 7-128 QAM, regime 7 / 8-256 QAM and regimen 2 / 3-8-PSK that are applied as an entry. As shown in Fig. 4, the demapping device 310 comprises the random access memory (RAM) 400 of the I channel, the RAM 402 of the Q channel, the RAM 404 of the remaper, the logic means 406 of demapping 8-PSK and the MUX multiplexer selections 408. The 2-bit code from the output of the convolutional encoder 308 of mode 1/2, of FIG. 3, is applied as a first input to the RAM 400 of the I channel, the RAM 402 of the Q-channel, the RAM memory 404 of the remaper and the logical means 406 of desmapeador 8-PSK. The 6 bits of the 12-bit output of the delay logic 312 of FIG. 3, which show the component I of the position in the plane I, Q of the received symbol, are applied as a second input to the RAM 400 of the I channel The 6 bits of the 12-bit output of the delay logic 312 displaying the Q component of the position in the I, Q plane of the received symbol are applied as a second input to the Q-channel RAM 402. bits of the 12-bit output of delay logic 312 that manifest component I, as the 6 bits of the 12-bit output of the delay logic 312 that manifest the Q component of the position in the plane I, Q of the received symbol, are respectively applied as the second and third inputs to the logic means 406 of the demagover. -PSK. In addition, according to the selected code of the various QAM codes being received, each of channel I RAM 400, Q channel RAM 402 and remaper RAM 404 is pre-loaded during an initialization phase with the look-up tables Precomputed, programmable I and Q, coming from the microcontroller interface 204, applied as a control input thereto. Query tables are not required for the logical means 406 of the 8-PSK demapping device. Additionally, a control input is applied from the microcontroller interface 204 to the selections of MUX 408 to select (1) both 3-bit outputs of the channel I and Q channel RAMs 400 and 402.; (2) the 5-bit output of the remaper RAM 404 or (3) the 1-bit output of the logical media 406 of remapper 8-PSK. The 3-bit outputs of the RAMs 400 and 402 of channel I and channel Q are also applied, respectively, as the second and third inputs to the RAM 404 of remapper, while a 6-bit output, from the selections 408 of MUX is applied as an input to selection 316 of Figure 3. The 6-bit I component defines 64 different I (2") values, while the 6-bit Q component defines 64 different Q (26). the received symbol occupying a particular individual point in a series of 4096 data points (212) in the I, Q plane, however, the largest constellation of transmitted symbols (ie 256) QAM) constitute a series of only 256 symbols (2nd).

For the purposes of the present invention, this maximum constellation of 256 QAM, together with constellations less than 16 (24) QAM and 64 (26) QAM, which are even powers of two, constitute a first demapping category. The minor constellations 32 (25) QAM and 128 (27) QAM, which are odd powers of two, constitute a second demapping category, while the 8-PSK constellation by itself constitutes a third demapping category. Each of these three demapping categories is discussed later, in turn. The bit-to-symbol mapping, for each of the constellations of 16, 64 and 256 QAM, which belong to the first category, is arranged in a square grid. Consider first the bit-to-symbol mapping for the 16 QAM constellation, which is shown below in table 1, both in octal and in binary representation.

TABLE 1 OCTAL BINARY OCTAL BINARY OCTAL BINARY OCTAL BINARY 00 000-000 01 000-001 04 000-100 05 000-101 02 000-010 03 000-011 06 000-110 07 000-111 001-000 11 001-001 14 001-100 15 001-101 12 001-010 13 001-011 16 001-110 17 001-111 The two lowest significant digits, which are shown in the bold type, of each binary representation of each constellation symbol, are determined by the respective binary values of the 2-bit input to each of the RAMs 400 and 402 of channel I and channel Q, from encoder 308. As indicated in Table 1, the two lowest significant binary digits of the value 00 correspond to a minor significant octal digit, of 0 or 4; and the two lowest significant binary digits of the value 01 correspond to a minor significant octal digit, of 1 or 5; the two lowest significant binary digits of value 10 correspond to a minor significant octal digit, of either 2 or 6, and the two minor binary significant digits, of value 11, correspond to a significant octal digit less than 3 or 7. Additionally , the lowest binary significant digits 00 (0 or 4 of octal minor significant digit) occupy only cells in the odd and odd columns of table 1; the lowest binary significant digits 01 (minor octal significant digit 1 or 5) occupy only cells in the odd and even columns of table 1; the lowest binary significant digits 10 (minor octal significant digit 2 or 6) occupy only cells in even rows and odd columns of table 1; and the lowest binary significant digits 11 (minor octal significant digit 3 or 7) occupy only cells in the odd and odd columns of table 1. In this way, the series of 16 symbols in the constellation of table 1 can be effectively divided to separate sub-series 00, 01, 10 and 11 of four symbols each, as shown, respectively, in the following tables 1-00, 1-01, 1-10 and 1-11. BOX 1-00 TABLE 1-01 TABLE 1-10 TABLE 1-11 In each cell of tables 1-00, 1-01, 1-10 and 1-11, the binary value of each of the bits Q and I is equal to the binary value of each of the two bits Significant lower values of the corresponding cell in Table 1, shown in normal type (that is, the 2 bits immediately to the left of the bits shown in bold in each cell of Table 1). This results in the binary values Q and I of the sub-series 00, 01, 10 and 00 shown in the corresponding cells of the respective tables 1-00, 1-01, 1-10 and 1-11 being equal between yes. In addition, as indicated in tables 1-00, 1-01, 1-10 and 1-11, the bit-to-symbol mapping has been selected to directly provide a binary gray code mapping where the respective components I and Q of each symbol in frame I, Q remain independent of each other. Thus, in the horizontal direction (ie, component I), from left to right, the values represented by the binary gray code are 0 and 1 in each of the tables 1-00, 1-01, 1-10 and 1-11. Similarly, in the vertical direction (ie, the Q component) from top to bottom, the values represented by the binary gray code are also 0 and 1 in each of the tables 1-00, 1-01, 1- 10 and 1-11. The bit-to-symbol mapping selected for each of the 64 and 256 QAM constellations of the first category (shown in octal representation in the following tables 2 and 3) is similar, in principle, in bit-to-symbol mapping selected for the 16 QAM constellation described above.

TABLE 2 OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL 00 01 04 05 14 15 10 11 02 03 06 07 16 17 12 13 21 24 25 34 35 30 31 22 23 26 27 36 37 32 33 60 61 64 65 74 75 70 71 62 63 66 67 76 77 72 73 40 41 44 45 54 55 50 51 42 43 46 47 56 57 52 53 TABLE 3 OCTAL REPRESENTATION 000 001 004 005 014 015 010 011 030 031 034 035 024 025 020 021 002 003 006 007 016 017 012 013 032 033 036 037 026 027 022 023 040 041 044 045 054 055 050 051 070 071 074 075 064 065 060 061 042 043 046 047 056 057 052 053 072 073 076 077 066 067 062 063 140 141 144 145 154 155 150 151 170 171 174 175 164 165 160 161 142 143 146 147 156 157 152 153 172 173 176 177 166 167 162 163 100 101 104 105 1J4 115 110 111 130 131 134 135 124 125 120 121 102 103 106 107 116 117 112 113 132 133 136 137 126 127 122 123 300 301 304 305 314 315 310 311 330 331 334 335 324 325 320 321 302 303 306 307 316 317 312 313 332 333 336 337 326 327 322 323 340 341 344 345 354 355 350 351 370 371 374 375 364 365 360 361 342 343 346 347 356 357 352 353 372 373 376 377 366 367 362 363 240 241 244 245 254 255 250 251 270 274 274 275 264 265 260 261 242 243 246 245 256 257 252 253 272 273 276 277 266 267 262 263 200 201 204 205 214 215 210 211 230 231 234 235 224 225 220 221 202 203 206 207 216 217 2 12 213 232 233 236 237 226 227 222 223 Specifically, the octal representation shown in each cell of tables 2 and 3 can be converted to binary representation, whereby (1) the least significant 2 bits of said converted binary representation of table 2 effectively divide the series of 64 symbols to sub -series separated 00, 01, 10 and 11 of 16 symbols each; and (2) the two least significant bits of said converted binary representation of Table 3 effectively divide the series of 256 symbols into separate sub-series 00, 01, 10 and 11, of 64 symbols each. In each cell of the sub-series 00, 01, 10 and 11 of the series in Table 2, the binary value of each of the bits Q and I is equal to the binary value of each of the 4 significant bits in the representation binary of the corresponding cell in Table 2, which are immediately higher than the 2 lowest significant bits in the binary representation of that corresponding cell in Table 2. Similarly, in each cell of sub-series 00, 01, 10 and 11 of the series in Table 3, the binary value of each of the bits Q and I is equal to the binary value of each of the 6 significant bits in the binary representation of the corresponding cell in Table 3, which are immediately larger than the two lower significant bits in the binary representation of that corresponding cell in Table 3. This results in the binary values Q and I of the sub-series 00, 01, 10 and 00 of each of the series in Table 2 and box 3 are equal to each other . Additionally, the bit-to-symbol mapping in each of the frames 2 and 3 has been selected to directly provide a binary gray code mapping in which the respective I and Q components of each symbol in the I, Q plane remain independent between yes. Thus, in the horizontal direction (ie, component I), from left to right, the values represented by the binary gray code are 0, 1, 2 and 3 in each of the sub-series 00, 01, 10 and 00 of the series in table 2; and the values represented by the binary gray code are 0, 1, 2, 3, 4, 5, 6 and 7 in each of the sub-series 00, 01, 10 and 00 of the series in Table 3. Similarly, in the vertical direction (ie, the Q component), from top to bottom, the values represented by the binary gray code are 0, 1, 2 and 3 in each of the sub-series 00, 01, 10 and 00 of the series of table 2, and the values represented by the binary gray code are 0, 1, 2, 3, 4, 5, 6 and 7 in each of the sub-series 00, 01, 10 and 00 of the series of the table 3. Returning to figure 4, the channel RAM 400 1 is initially pre-loaded by interface 204 of the microcontroller with a 1-bit look-up table in the case of 16 QAM (table 1), with a 2-bit look-up table in the case of 64 QAM (table 2) and with a 3-bit query table in the case of 256 QAM (Table 3). Similarly, the Q channel RAM 402 is initially preloaded by the microcontroller 204 with a 1-bit look-up table in the case of 16 QAM (Table 1), with a 2-bit look-up table in the case of 64 QAM ( Table 2) and with a 3-bit query table in the case of 256 QAM (Table 3). The query box of the RAM 400 of channel 1, in response to being directed by the 6-bit I input from the delay logic 312 and the 2-bit I input from the convolutional encoder 308, reads component I of the code binary gray of that column of constellation symbols that is closer in the distance in I direction (horizontal) to the position of component I of the received, delayed symbol. Similarly, the look-up table of the Q-channel RAM 402, in response to being directed by the 6-bit input Q from the delay logic 312 and the 2-bit input I from the convolutional encoder 308, reads the code Q. In the case of the first category (ie, 16, 64 and 256 QAM) the MUX selections 408 are operated by the control input to the multiplexer, coming from the interface 204 of the microcontroller, to carry forward the read outputs of the respective look-up table, coming from the I-channel RAM 400 and the Q-channel RAM, as an input to the selection 316 of Figure 3. It will be noted that the identity of the sub-series 00, 01, 10 and 11 is lost in the read outputs of 4 channel 400 RAM I and ca.1 S Q. RAM, sent through selection 316 of figure 3 to a downstream portion of the multi channel receiver. However, as shown in FIG. 3, the 1-bit output of Viterbi decoder 306 is also sent through selection 316 of FIG. 3 to the portion located downstream of the multi-channel receiver. Since the 2-bit output of the convolutional encoder 308 (which is used in the frame demapping 310 to define the sub-series 00, 01, 10 and 11) is derived from the 1-bit output of the Viterbi decoder 306, the sub-series 00, 01, 10 and 11 can again be derived in the downstream portion from the 1-bit output of the Viterbi decoder that is sent to it. The constellations 32 (2J) and 128 (2 ') QAM belong to category 2. The constellations of category 2, because they consist of an odd power of 2 symbols, the symbols are arranged in a transverse grid instead of a square grid. In addition, the bit-to-symbol mapping of the constellation series of category 2 is not capable of directing the binary gray code mapping or of providing it directly for its sub-series 00, 01, 10 and 11. Therefore, it is requires remapping the bitmap to symbol of the sub-series 00, 01, 10 and 11 of category 2 to obtain the binary gray code mapping of the symbols of each sub-series. In this sense, the following table 4 shows, in octal representation, the bit-to-symbol mapping of the cross grid arrangement for the 32 QAM constellation series and the tables 4-00, 4-01, 4-10 and 4- 11 show, respectively, the different remaps of each of the sub-series 00, 01, 10 and 11 of the constellation series 32 QAM. Similarly, the following table 5 shows in octal representation the bit-to-symbol mapping of the cross grid arrangement for the constellation series of 128 QAM and the table 5a shows the common remapping of each of the sub-series 00, 01, 10 and 11 of the constellation series 128 QAM.

TABLE 4 OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL 30 21 20 31 17 26 07 06 27 16 11 34 01 00 35 10 13 36 03 02 37 12 24 05 04 25 14 32 23 22 33 TABLE 4-00 Binary Binary Binary Binary Binary Binary 1100 1101 1111 - > 110 100 010 0100 0101 0111 - > 111 000 010 0000 0001 0011 - > 101 001 011 TABLE 4 -01 3inary Binary Binary Binary Binary Binary 1100 1101 1111 - > 100 100 110 0100 0101 0111 - > 010 000 111 0000 0001 0011 - > 111 001 101 TABLE 4 -10 Binary Binary Binary Binary Binary Binary 1100 1101 1111 - > 101 001 011 0100 0101 0111 - > 111 000 010 0000 0001 0011 - > 110 100 010 TABLE 4 -11 Binary Binary Binary Binary Binary Binary 1100 1101 1111 011 001 101 0100 0101 0111 - > 010 000 111 0000 0001 0011 100 100 110 TABLE 5 3TAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL OCTAL 114 115 104 105 124 125 120 121 116 117 106 107 126 127 122 123 100 101 000 001 004 005 024 025 020 021 134 135 102 103 002 003 006 007 026 027 022 023 136 137 110 111 010 011 014 015 034 035 030 031 130 131 112 113 012 013 016 017 036 037 032 033 132 133 150 151 050 051 054 055 074 075 070 071 170 171 152 153 052 053 056 057 076 077 072 073 172 173 154 155 040 041 044 045 064 065 060 061 160 161 156 157 042 043 046 047 066 067 062 063 162 163 140 141 144 145 164 165 174 175 L42 143 146 147 166 167 176 177 TABLE 5a OCTAL REPRESENTATION 70 71 73 72 76 77 > 23 23 21 25 24 27 60 61 63 62 66 67 20 00 01 05 04 27 21 23 22 26 27 - > 22 02 03 07 06 26 31 33 32 36 37 - > 32 12 13 17 16 36 11 13 12 16 17 - > 33 10 11 15 14 34 01 03 02 06 07 - > 33 30 31 35 37 37 In tables 4 and 5 (in tables 1, 2 and 3) the cells in which the least significant digit of the octal representation is a 0 or a 4 belong to the sub-series 00, the cells in which the least significant digit of the octal representation is a 1 or a 5 belong to sub-series 01; the cells in which the least significant digit of the octal representation is a 2 or a 6 belong to the sub-series 10 and the cells in which the least significant digit of the octal representation is a 3 or a 7 belong to the sub -series 11. If the octal representation of each cell in tables 4 and 5 is converted to the binary representation, those binary significant bits greater than the lower 2 significant binary bits constitute the output of the remaper RAM 404. The remaper RAM 404 is initially preloaded by the microcontroller interface 204 with a 3-bit look-up table in the case of 32 QAM (table 4) and with a 5-bit look-up table in the case of 128 QAM (table 5). ). In the case of 32 QAM, the remapper lookup table is read in response to a 2-bit output from the I-channel RAM 400 applied as a first input to it, a 2-bit output from RAM 402 of channel Q, applied as a second input to it, and a 2-bit output from convolutional encoder 308, applied as a third input to it. In the case of 128 QAM, the remapper lookup table is read in response to a 3-bit output from the I-channel RAM 400, applied as a first input to it, and a 3-bit output from the RAM 402 of channel Q, applied as a second input to it. The respective binary values of the 2-bit output from the look-up table of each of the channel 400 RAMs 400 of channel I and RAM 402 for each of the sub-series 00, 01, 10 and 11 of the series of the constellation 32 QAM, is limited to only 3 determined values of the four possible binary values that can assume 2 bits. Specifically, as shown in the left portion of each of the tables 4-00, 4-01, 4-10 and 4-11, the respective outputs of the 2 bits of the RAMs 400 and 402 provide a binary mapping of 4. binary bits, from bit to symbol, of a certain portion of 9 symbols of a possible constellation of 16 symbols for each of the sub-series 00, 01, 10 and 11, with the 2 least significant bits of the 4 binary bits of each cell of each sub-series that is the 2-bit component I from RAM 400, and the 2 most significant bits of the 4 binary bits which are the 2-bit Q component from RAM 402. As shown in the left portion of each of the tables 4-00, 4-01, 4-10 and 4-11, the mapping of 4 binary bits, from bit to symbol, for each of the sub-series 00, 01, 10 and 11, is equal to the others. The remaper 404 remaps the map of 4 binary bits, from bit to symbol, for each one of these sub-series 00, 01, 10 and 11 to a different mapping of 3 binary bits, bit by bit, for each one of these four sub-series as shown, respectively, in the right portion of each of the tables 4-00, 4-01, 4-10 and 4-11. A different remapping of 3 binary bits, bit by bit, for each of these four sub-series, is necessary, due to the respective shapes of the eight cells of the eight-cell series of the 32 QAM symbol constellation (shown in table 4) that constitutes each of these four sub-series is not symmetrical with respect to the others. Additionally, because the mapping of 3 binary bits, from bit to symbol, for each of these four sub-series shown, respectively, in the right portion of each of the tables 4-00, 4-01, 4- 10 and 4-11 comprises nine cells instead of the eight appropriate cells, it is necessary to duplicate the mapping of 3 binary bits, bit by bit, into a pair of two adjacent cells of the nine cells of each of the four sub-cells. series, with each pair of the two adjacent cells occupying a single corner of each of the tables 4-00, 4-01, 4-10 and 4-11. The loss in operation due to this duplication is considered to be negligible. In the case of the constellation series 128 QAM, the respective binary values of the 3-bit output from the look-up table of each of channel I RAM 400 and Q channel RAM 402 for each of the sub-stations. series 00, 01, 10 and 11 thereof, is limited to that part of the binary bit-to-symbol 6-bit mapping, which comprises the 36 symbols shown in the octal representation in the left portion of the frame 5a. The remaper memory 404 remaps the 36 symbols shown in the octal representation in the left portion of the frame 5a, to the 36 symbols shown in the octal representation in the right portion of the frame 5a, for each of the sub-series 00, 01 , 10 and 11 of the 128 QAM constellation series. The same bit-to-symbol remapping can be used for each of these four sub-series because the respective shapes of the 32 cells of the symbol constellation series 128 QAM (shown in Table 5) which constitutes each of These four sub-series are symmetrical with respect to each other. Additionally, because the bit-to-symbol mapping for each of these four sub-series shown in the right portion of Table 5a comprises 36 cells, instead of the 32 appropriate cells, it is necessary to duplicate the bitmap to symbol of 3 binary bits in four pairs of two adjacent cells of the 36 cells in which each of the four pairs of two adjacent cells occupies a different corner of the four corners of the square 5a. Again the functional loss due to this duplication is considered negligible.

Referring now to Figure 5, a bit-to-symbol mapping of 3 binary bits is shown for 8-PSK encoded in framing in the I, Q plane. As indicated, the symbols are symmetrically distributed around the origin IQ, with each of the symbols angularly displaced 22.5 ° or 67.5 ° with respect to the axis I. The mapping from bit to symbol is such that the two least significant binary digits divide the 8-PSK series of symbols to sub-series 00, 01, 10 and 11, where each sub-series includes two symbols. The binary value of the most significant bit of the three bits is used to differentiate between the two symbols in each of the four sub-series. Specifically, the binary value of the most significant bit of the 3 bits in the upper quadrants (ie, first and second) of the I, Q plane is "0" and the most significant bit value of the three bits in the lower quadrants (that is, third and fourth) of the I, Q plane is "1". Returning to Figure 4, the logical means 406 of the 8-PSK demapping does not use a look-up table directly to make the decision about which of the two symbols (I? Ql) and ^ 2 ^? in ^ a sub-series of the sub-series 00, 01, 10 and 11, selected by the 2-bit input from the convolutional encoder 308 to the logical means 406 of demapping 8-PSK, is closer to the data point (I, Q) of the received symbol determined by the I inputs of 6 bits and Q of 6 bits, from the delay logic 312 to the logical means 406 of the 8-PSK demapping device. The only operation that needs to be performed in order to make this decision can be decided by performing the following logic comparison by the logical means 406 of the 8-PSK demapping device: If I x I] _ < Q x Q2, then output = l; Otherwise, output = 0. You can implement this comparison using the query tables to perform the multiplications or you can perform an explicit multiplication. For the deviated 8-PSK constellation, shown in Figure 5, the multiplication values are all sines and cosines of 22.5 °. This reduces the products by 10, 22.5 ° = 4 (to a significant figure) and 10 cosine22 5 ° = 9 (to a single significant figure). Since I as Q are multiplied by the factor sine and cosine, a multiplication by 10 does not change the results of the comparison. A binary multiplication by 9 requires a displacement operation (without additional peripheral) and an adder. A binary multiplication by 4 is a simple displacement operation and does not require extra peripheral. Based on the comparison, the appropriate symbol of the two constellation symbols of the selected sub-series can be selected. In addition, it has been found that the losses due to rounding (that is, without using the exact values of sine and cosine) are negligible, since the decision regions are altered only in 4o in the worst case. This small difference makes very little difference in error performance (< 10 ~ 3 symbol error probabilities) in all regions of interest. A table of multiplications and displacements for each sub-series is detailed in the following table 6. TABLE 6 PRODUCT SUBSERIE 00 SUBSERIE 01 SUBSERIE 10 SUBSERIE 11 Jl +9 +4 -9 +4 Q2 -4 -9 -4 -9 The storage requirements for the fabric demapping mode of the present invention, shown in Figure 4, are minimal. RAM 400 and 402 of channel I and channel Q together need to store only 2x256x3 = 1.536 bits for all the modulation schemes described above. This is true because the I and Q components remain independent throughout the operation of each of the RAMs 400 and 402. Using conventional framing demapping techniques, where the I and Q components do not remain independent throughout the operation, it would need a read only memory (ROM) that had a storage capacity of about 8, 000 bits for all the different modulation schemes described above. For the 32 and 128 QAM modulation schemes described above, another 64 x 5 = 320 of RAM is required by the remaper RAM 404 of FIG. 4. Therefore, the total storage need for the framing demapping mode of the present invention, shown in Figure 4, is 1.536 + 320 = 1,856 bits. It is evident that the framework demapper for a convolutional decoder of the present invention can be generalized to a first case in which the maximum constellation lattice code QAM, which is an even power of 2, includes 2 ^ v symbols arranged in a square grid, where y is a positive integer that has a value of at least 2; and a second class in which the constellation framework code QAM, in which the constellation framework code QAM maximum, which is an odd power of 2 includes 2Z symbols arranged in a transverse grid, where z is a positive integer odd that has a value of at least 5. The first case includes the constellation fabric codes 16, 64, and 256 QAM, described above, and any QAM constellation fabric code of more than 256 (ie, where and has a value of more than 4). The second case includes the 32 and 128 QAM constellation fabric codes described above and any QAM constellation fabric code greater than 128 (ie, where z is a positive, odd integer that has a value that is greater than 7). In the first case, when the symbols are arranged in a square grid, a value of y less than 4 does not result in any loss in operation. However, in the second case, when the symbols are arranged in a transverse grid, a value of z greater than 7 does result in some loss in operation, because the remapping requires the multiplication of the bits that map the cells corner of the grid of cells remapped in the constellation sub-series (for example, 2 2 = 4 duplications in each of the four corners of the grid of 12 x 12 for a sub-series of 128 remapped symbols (2 ' ) of a constellation of 512 symbols (29), or 4 x 4 = 16 duplications in each of the four corners of the grid of 24 x 24 for a sub-series of 512 remapped symbols (29) of a constellation of 2,048 symbols (2 - -), by way of examples). Further generalizing, the number of different values of the component I the number of different values of the Q component of the received symbols that can be applied, respectively, as inputs to the I-channel RAM 400, to the Q-channel RAM 402 and to the logical means 406 of the 8-PSK demapping device, it is in any case a positive integer 2X, where x > y and x > z / 2. Although the RAM 400 of channel I, the RAM 402 of channel Q and the RAM 404 of the remapper are shown as separate items, it should be understood that in practice any two or all three of these can be combined. these RAM memories in a single physical device.

Claims (9)

NOVELTY OF THE INVENTION CLAIMS

1. - In a convolutional decoder (200, figures 2 and 3) of a plurality of pragmatic framework codes, each of which is defined by a plurality of convolutionally encoded symbol packets, applied as digital input signals in phase (I) and in quadrature phase (Q) to the same; wherein said pragmatic framework codes comprise a different code for each series of symbols constellation in the I, Q plane that includes an even power of two of the number of symbols arranged in a bit-by-symbol, square grid mapping, including the maximum constellations of said constellations of square grid symbol 22v symbols; where y is a first positive integer that has a given value of at least 2; and wherein the convolutional decoder includes a framework demapper (310) for demapping each of the plurality of pragmatic framework codes; the improvement characterized in that (1) the bit-to-symbol mapping of the square grid of each constellation series is such that the alternative cells of the odd rows of the square grid define a first sub-series of symbols; the remaining cells of the odd rows of the square grid define a second sub-series of symbols; the alternative cells of the even rows of said square grid define a third sub-series of symbols; and the remaining cells of the even rows of the square grid define a fourth sub-series of symbols; and (2) the frame demapping device is characterized by: a channel I random access memory (RAM 400) having an effective depth of locations of 2 * x + 2 'storage locations, where x is a second positive integer that has a given value, greater than the first positive integer; each storage location has an effective amplitude at least sufficient to store an annotation of a look-up table that defines I, and that has y-bits; a channel Q RAM (402) having an effective depth of 2 x + 2 'storage locations; each storage location having an effective width at least sufficient to store an annotation of a look-up table defining Q, which has y-bits; first means (312) for applying a first x-bit input to said channel I RAM to define the value of said digital input signal in phase (I) and to apply a second x-bit input to the channel RAM Q to define the value of the quadrature digital input signal (Q); second means (308) to apply a 2-bit input to both channel I RAM and Q channel RAM to define a selected sub-series of said four sub-series, in accordance with the binary value of the input of 2 bits applied; third means (204, FIGS. 2 and 3), for preloading the look-up table of channel I RAM, according to a selected series of said series of constellation symbols, such that the bit mapping of component I of that symbol of the selected sub-series of said four sub-series of the selected series of the constellation series that is closest in value to the value defined by the digital input signal in phase (I) to the channel I RAM, be read as the output of channel I RAM; middle rooms (204) for preloading the lookup table of the channel Q RAM according to a selected series of said series of constellation symbols, such that the bit mapping of the Q component of that symbol of the sub-series selected from the four sub-series of the selected series of the constellation series that is closest in value to the value defined by the digital quadrature input signal (Q) to the Q channel RAM to be read, at the output of said Channel RAM Q. 2.- The convolutional decoder defined in claim 1, further characterized in that: the bit-to-symbol mapping of the square grid of each series of constellation is such that the third means employ binary bits coded in gray, for form the bitmap of the pre-loaded query table of channel I RAM; and the four means employ binary gray code bits to form the bitmap of the pre-loaded lookup table of the Q channel RAM. 3. The convolutional decoder according to claim 2, further characterized by: the symbol series of constellation in the I, Q plane that include a pair power other than 2, of the number of symbols arranged in a square grid, include a constellation of 16 QAM symbols, a constellation of 64 QAM symbols and a constellation of 256 QAM symbols; the value of y is 3; and the value of x is 6. 4. The convolutional decoder defined in claim 1, further characterized in that: the plurality of pragmatic framework codes also comprise a separate code for each series of constellation symbols in the I, Q plane includes an odd power of 2, from the number of symbols arranged in a bitmap to cross grid symbol, including the largest of the transverse grid symbol constellations 2Z symbols; wherein z is a third positive integer having a given value of at least 5, such that the value x of the second positive integer is greater than the value of z / 2 and the bit-to-symbol mapping of the transverse grid of each series of constellation is such that the alternate cells of the odd rows of the transverse grid define a first sub-series of symbols; the remaining cells of the odd rows of the transverse grid define a second sub-series of symbols; the alternate cells of the even rows of the transverse grid define a third sub-series of symbols; and the remaining cells of the even rows of the transverse grid define a fourth sub-series of symbols; and where: the query table of channel I RAM, when preloaded by the third media according to the selected series of constellation series which is an odd power of two symbols (1) provides the same bit mapping a symbol for component 1 of each of the four subseries; and (2) this bit-to-symbol mapping comprises a given number of columns of a square grid, where the given number of columns is the maximum number of columns in only one of the four sub-series of the cross grid of the series selected from the constellation series of an odd power of two symbols; the query table of the channel Q RAM, when preloaded by the fourth means according to the selected series of the constellation series is an odd number of two symbols (1) provides the same bit-to-symbol mapping for the component Q of each of the four sub-series; and (2) this bit-to-symbol mapping comprises a given number of rows of a square grid in which the given number of rows is the maximum number of rows in only one of the four sub-series of the cross grid of the series selected from constellation series of odd power of two symbols; and the framework demapper further comprises (1) a remaper RAM (404), which responds to said 2-bit input; the output of the channel I RAM and the output of the Q channel RAM are applied as respective inputs thereto to remap the bit-to-square mapping of the symbols defined by component I present in the output of the channel I RAM and the Q component present in the output of the Q channel RAM, to a bitmap to square grid symbol at the output of the remaper, and said square grid of output of remaper includes both the symbol cells given which constitute any of said four sub-series, and at least one additional symbol cell located in at least one corner of the square grid of the remapper outlet; the bit mapping of said additional symbol cell is a duplicate of the bit mapping of a given symbol cell which is located contiguous with respect to said corner of the square grid; and (2) selects means (408) (a) that respond to the selected series of the constellation series which is an odd power of two symbols to forward the output of the remaper RAM as the output of the frame demapping device; and (b) responds to said selected series of the constellation series which is an odd power of two symbols to directly send forward the respective outputs of channel I RAM and Q channel RAM, such as the output of the lattice demaker . 5. The convolutional decoder defined in claim 4, further characterized in that: the plurality of series of constellation symbols includes a certain constellation series of an odd power of 2, of the number of symbols equal to 5; the output of the RAM of channel I consists of 2 bits that are expressly limited to only 3 of 4 possible binary values in which these 3 binary values define the three columns of a square grid of 3x3; the output of the RAM Q consists of 2 bits that are expressly limited to only 3 of 4 possible binary values, where these three binary values define the three rows of the square grid of 3x3; so as to derive a sub-series of eight non-symmetric symbols, located within a 3x3 square grid, which has a different bit-by-symbol mapping for each of the four sub-series at the output of the remaper; wherein the duplicate forms the bitmap of a single additional symbol cell for each of the four separate sub-series, and said individual additional symbol cell is located at a different corner of the four corners of the individual square gratings of 3x3, corresponding, respectively, to each of the four separate sub-series. 6. The convolutional decoder defined in claim 4, further characterized in that: the plurality of series of constellation symbols includes a given constellation series of a given odd power of two symbol numbers greater than 5; so that the symbols of each of the four sub-series of said determined constellation series, of a given odd power of two numbers of symbols greater than 5 are arranged in a transverse grid; the output of the RAM of channel I consists of a group of at least 3 bits, where the number of binary values expressed by said group of bits is expressly limited to the number k of columns in the transverse grid, of any of the four sub-series, where k is a positive integer quarter; the Q channel RAM output consists of a group of at least 3 bits, wherein the number of binary values expressed by said group of bits is expressly limited to the number k of rows in the transverse grid of any of the four sub -series; so as to derive a sub-series of transverse grid symbols, symmetrical, located within a square grid kxk, which has the same bit-to-symbol mapping for each of the four sub-series at the output of the remaper; wherein the duplicate forms the bitmap of at least one additional symbol cell located in each of the four corners of 4 the square grid kxk for each of the four sub-series. 7. The convolutional decoder defined in claim 4, further characterized in that: the bit-to-symbol mapping that appears in each of the outputs of the T channel RAM, the Q channel RAM and the remaper RAM consists of bits binaries encoded in gray. 8. The convolutional decoder defined in claim 7, further characterized in that: the series of constellation symbols in the plane I, Q that include a different power pair of 2 numbers of symbols arranged in a square grid include a QAM constellation of 16 symbols, a QAM constellation of 64 symbols and a QAM constellation of 256 symbols; the series of constellation symbols in the I, Q plane that include an odd power different from two numbers of symbols arranged in a transverse grid include a QAM constellation of 32 symbols and a QAM constellation of 128 symbols; the value of y is 3; the value of z is 7; and the value of x is 6. 9. The convolutional decoder defined in claim 8, further characterized in that: said plurality of pragmatic framework codes also comprise a separate code for a series of 8 8-PSK constellation symbols in the plane I, Q, wherein said 8 symbols are symmetrically radially distributed around the origin of the plane I, Q, each of the 8 symbols being angularly deviated substantially at 22.5 ° with respect to an axis of the plane I, Q; and the series of 8 8-PSK constellation symbols has a 3-bit bit-to-symbol mapping, so that the 8-PSK constellation series is divided into 4 sub-series of two symbols each, according to the value binary expressed by the two least significant bits of said three bits, and the two symbols of each of these four sub-series differ from each other according to the binary value expressed by the highest significant bit of said three bits; the lattice demapper additionally comprises a logical means (406) of demapping 8-PSK, which responds to: (1) the first x-bit input, which is applied as a first input thereto, to define the value of said signal digital input in phase (I); (2) the second x-bit input being applied as a second input thereto to define the value of the quadrature digital input signal (Q); and (3) applying the 2-bit input as a third input to it to select one of the four sub-series of said 8-PSK constellation series, according to the binary value expressed by the 2-bit input that is being applying and in response to the first, second and third inputs thereto, said 8-PSK demapping logic means derives a 1-bit output thereof that expresses the binary value of said highest significant bit of the three bits of the bitmap a symbol, which is indicative of one of the two symbols of the selected sub-series of the four sub-series of the 8-PSK constellation, which is closest in distance (I + Q) to the position of a symbol in said plane I, Q defined by the respective values of the digital input signal in phase (I), applied to it as a first input, and the quadrature digital input signal (Q), applied to it as a second input; and said selection means also responding to a selection of the 8-PSK constellation series which sends said 1-bit output from the 8-PSK demapping logic means as an output of the framing demapper. 10. The convolutional decoder defined in claim 9, further characterized in that: the bit-to-symbol mapping of the 8 constellation symbols 8-PSK is such that a symbol in the first quadrant of the I, Q plane is oriented substantially at 22.5 ° with respect to axis I it is mapped with a binary value of 000; a symbol in the first quadrant of the I, Q plane oriented substantially at 22.5 ° with respect to the Q axis is mapped with a binary value 001; a symbol in the second quadrant of the plane I, Q oriented substantially 22.5 ° with respect to the axis I is mapped with the binary value 010; a symbol in the second quadrant I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with a binary value 011; a symbol in the third quadrant of the I, Q plane oriented substantially 22.5 ° with respect to the axis I, is mapped with a binary value 100; a symbol in the third quadrant of the I, Q plane, oriented substantially at 22.5 ° with respect to the Q axis, is mapped with the binary value 101; a symbol in the fourth quadrant I, Q, oriented substantially at 22.5 ° with respect to the axis I, is mapped with the binary value 110; and a symbol in the fourth quadrant of the plane I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with the binary value 111; and the 8-PSK demapping logic means includes means for deriving a binary value of "1" for the 1-bit output from it only if the product of the numerical value of the digital input signal in phase (I), multiplied by the numerical value of 1 ^ is less than the product of the numerical value of said quadrature digital input signal (Q), multiplied by the numerical value of Q2 ¡where the numerical value of I-j_ is 9 for the sub-series 00; 4 for sub-series 01, -9 for sub-series 10 and -4 for sub-series 11; and the numerical value of Q2 is -4 for the sub-series 00, -9 for the sub-series 01, -4 for the sub-series 10 and -9 for the sub-series 11. 11.- The convolutional decoder defined in claim 10, further characterized in that: the convolutional decoder is a component of a multi-channel receiver (100, FIG. 1). 1

2. The convolutional decoder defined in claim 11, further characterized in that: the multi-channel receiver is a digital television receiver for receiving compressed digital television data, corrected in sending error, which is transmitted to it. 1

3. In a convolutional decoder (200, figures 2 and 3) of a plurality of pragmatic framework codes, each of which is defined by a series of convolutionally coded symbol packets, applied as digital input signals in phase ( I) and in quadrature phase (Q) to it; wherein the plurality of pragmatic framework codes comprise a separate code for each series of constellation symbols in the I, Q plane that includes an odd power of 2 number of symbols arranged in a bitmap to cross grid symbol, including the greater constellation of said constellations of transverse grid symbols 2Z symbols, wherein z is a first positive integer having a given value of at least 5; and wherein the convolutional decoder includes a framework demapper (310) for demapping each of the plurality of pragmatic framework codes; the improvement characterized in that: (1) the bit-to-symbol mapping of the transverse grid of each series of constellation is such that the alternative cells of the odd rows of the transverse grid define a first sub-series of symbols; the remaining cells of the odd rows of the transverse grid define a second sub-series of symbols, the alternative cells of the even rows of said transverse grid define a third sub-series of symbols, and the remaining cells of the even rows of the transverse grid define a fourth sub-series of symbols; and (2) the framing demapper is characterized by: a random access memory (RAM) (400), of channel I, having an effective depth of 2 'x +' storage locations; wherein x is a second positive integer having a given value, greater than half of said first positive integer; each storage location has an effective amplitude at least sufficient to store an annotation of a lookup table defining I, of b-bits, where b = z / 2 + l / 2; a RAM (402) of channel Q having an effective depth of 2 ^ xl2 ^ storage locations; each storage location having an effective amplitude at least sufficient to store an annotation of a look-up table defining Q, of b-bits; first means (312) to apply a first x-bit input to the channel I RAM to define the value of the digital input signal in phase (I) and to apply a second x-bit input to the channel RAM Q, to define the value of the quadrature digital input signal (Q); second means (308) to apply a 2-bit input to both channel I RAM and Q channel RAM to define a selected sub-series of said four sub-series, in accordance with the binary value of the input of 2 bits applied; third means (204, figures 2 and 3) to preload the look-up table of channel I RAM according to a selected series of said constellation series, of an odd power of two symbols, such that the bit mapping of the component I of that symbol of the selected sub-series of said four sub-series of the selected series of said constellation series that is closest in value to the value defined by the digital input signal in phase (I) to the RAM of channel I, be read as the output of channel I RAM to (1) provide the same bit-by-symbol mapping for component I of each of the four sub-series; and (2) the bit-to-symbol mapping comprises a given number of columns of a square grid, where the given number of columns is the maximum number of columns in only one of the four sub-series of the transverse grid of the series selected from said constellation series of an odd power of two symbols; means rooms (204) for preloading the look-up table of the channel Q RAM according to a selected series of said constellation series of an odd power of two symbols, such that the bits mapping the Q component of that symbol of the selected sub-series of the four sub-series of the selected series of said constellation series that is closest in value to the value defined by the quadrature digital input signal (Q) to the Q channel RAM, are read as the Q channel output to: (1) provide the same bit-to-symbol mapping for the Q component of each of the four sub-series; and (2) this bit-to-symbol mapping comprises a given number of rows of a square grid, where the given number of rows is the maximum number of rows in a single of the four sub-series of the cross grid of the series selected from the constellation series of an odd power of two symbols; and a RAM (404) of remaper that responds to the 2-bit input; the output of the channel I RAM and the Q channel RAM output being applied as respective inputs to it to remap the bit-to-symbol mapping of the square symbol grid defined by both the component i present in the output of the Channel RAM T as per the component Q present in the output of the channel Q RAM, towards a bitmap to square grid symbol, in the output of the remaper; said square output grid of the remapper includes both the given symbol cells constituting any of the four sub-series as well as at least one additional symbol cell located at least one corner of the square outlet grid of remapper; the bits that map said additional symbol cell are a duplicate of the bits that map a given symbol cell, which is located contiguous with respect to the corner of said square grid. 1

4. The convolutional decoder defined in claim 13, further characterized in that: the plurality of series of constellation symbols includes a series of constellation of an odd power of two number of symbols equal to 5; the output of the RAM of channel I consists of 2 bits that are limited to express only 3 of 4 possible binary values in which these three binary values define the three columns of a square grid of 3x3; the channel Q RAM output consists of 2 bits that are limited to express only 3 of 4 possible binary values in which these three binary values define the three rows of said 3x3 square grid; so that a sub-series of 8 symbols is derived, not symmetric, located within a 3x3 'square grid, which has a different bit-to-symbol mapping for each of the four sub-series at the output of the remaper; wherein the duplicate bits map a single additional symbol cell for each of the four separate sub-series, and the individual additional symbol cell is located at a different corner of said four corners of the individual 3x3 square gratings, which correspond respectively to each of the four separate sub-series. 1

5. The convolutional decoder defined in claim 13, further characterized in that: the plurality of series of constellation symbols includes a given constellation series of a given odd power of 2 number of symbols greater than 5, so that the symbols of each of the four sub-series of said determined constellation series of an odd power of 2 number of symbols greater than 5, are arranged in a transverse grid; the output of the RAM of channel I consists of a group of at least 3 bits, where the number of binary values expressed by said group of bits is expressly limited to the number k of columns in the transverse grid, of any of the four sub-series, where k is a positive integer quarter; the Q channel RAM output consists of a group of at least 3 bits, wherein the number of binary values expressed by said group of bits is expressly limited to the number k of rows in the transverse grid of any of the four sub -series; so as to derive a sub-series of transverse grid symbols, symmetrical, located within a square grid kxk, which has the same bit-to-symbol mapping for each of the four sub-series at the output of the remaper; wherein the duplicate forms the bitmap of at least one additional symbol cell located in each of the four corners of the square grid kxk for each of the four sub-series. 1

6. The convolutional decoder defined in claim 13, further characterized in that: the bit-to-symbol mapping that appears in each of the channel I RAM outputs, the Q channel RAM and the remaper RAM consists of bits binaries encoded in gray. 1

7. The convolutional decoder defined in claim 16, further characterized in that: the series of constellation symbols in the plane I, Q that include a different power pair of 2 numbers of symbols arranged in a square grid include a QAM constellation of 16 symbols, a QAM constellation of 64 symbols and a QAM constellation of 256 symbols; the series of constellation symbols in the I, Q plane that include an odd power different from two numbers of symbols arranged in a transverse grid include a QAM constellation of 32 symbols and a QAM constellation of 128 symbols; the value of z is 7; and the value of x is 6. 1

8. The convolutional decoder defined in claim 17, further characterized in that: said plurality of pragmatic framework codes also comprise a separate code for a series of 8 8-PSK constellation symbols in the plane I, Q, where said 8 symbols are distributed radially symmetrically around the origin of the plane I, Q, each of the 8 symbols being angularly deviated substantially at 22.5 ° with respect to an axis of the plane I, Q; and the series of 8 8-PSK constellation symbols has a 3-bit bit-to-symbol mapping, so that the 8-PSK constellation series is divided into 4 sub-series of two symbols each, according to the value binary expressed by the two least significant bits of said three bits, and the two symbols of each of these four sub-series differ from each other according to the binary value expressed by the highest significant bit of said three bits; the lattice demapper additionally comprises a logical means (406) of demapping 8-PSK, which responds to: (1) the first x-bit input, which is applied as a first input thereto, to define the value of said signal digital input in phase (I); (2) the second x-bit input being applied as a second input thereto to define the value of the quadrature digital input signal (Q); and (3) applying the 2-bit input as a third input to it to select one of the four sub-series of said 8-PSK constellation series, according to the binary value expressed by the 2-bit input that is being applying and in response to the first, second and third inputs thereto, said 8-PSK demapping logic means derives a 1-bit output thereof that expresses the binary value of said highest significant bit of the three bits of the bitmap a symbol, which is indicative of one of the two symbols of the selected sub-series of the four sub-series of the 8-PSK constellation, which is closest in distance (I + Q) to the position of a symbol in said plane I, Q defined by the respective values of the digital input signal in phase (I), applied to it as a first input, and the quadrature digital input signal (Q), applied to it as a second input; and said selecting means (408) (a) also responding to the selected series of said constellation series which is an odd power of 2 symbols to send the output of the remaper RAM, such as the output of the framing demayer and (b) which responds to a selection of the 8-PSK constellation series that sends said 1-bit output from the 8-PSK demapping logic means as an output of the framing demapper. 1

9. The convolutional decoder defined in claim 18, further characterized by: bit mapping a symbol of the 8 symbols of the series of 8-PSK constellation is such that a symbol in the first quadrant of the I, Q plane oriented substantially at 22.5 ° with respect to axis I it is mapped with a binary value of 000; a symbol in the first quadrant of the I, Q plane oriented substantially at 22.5 ° with respect to the Q axis is mapped with a binary value 001; a symbol in the second quadrant of the plane I, Q oriented substantially 22.5 ° with respect to the axis I is mapped with the binary value 010; a symbol in the second quadrant I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with a binary value 011; a symbol in the third quadrant of the I, Q plane oriented substantially 22.5 ° with respect to the axis I, is mapped with a binary value 100; a symbol in the third quadrant of the I, Q plane, oriented substantially at 22.5 ° with respect to the Q axis, is mapped with the binary value 101; a symbol in the fourth quadrant I, Q, oriented substantially 22.5 ° with respect to the axis I, is mapped with the binary value 110; and a symbol in the fourth quadrant of the plane I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with the binary value 111; and the 8-PSK demapping logic means includes means for deriving a binary value of "1" for the 1-bit output from it only if the product of the numerical value of the digital input signal in phase (I), multiplied by the numerical value of I-i is less than the product of the numerical value of said quadrature digital input signal (Q), multiplied by the numerical value of Q2; where the numerical value of 1 ^ is 9 for sub-series 00; 4 for sub-series 01, -9 for sub-series 10 and -4 for sub-series 11; and the numerical value of Q2 is -4 for the sub-series 00, -9 for the sub-series 01, -4 for the sub-series 10 and -9 for the sub-series 11. 20.- In a convolutional decoder of a pragmatic framework code defined by a series of convolutionally encoded symbol packets, applied as digital input signals in phase (I) and in quadrature phase (Q); wherein the pragmatic framework code comprises a series of 8 8-PSK constellation symbols, in the I, Q plane, wherein said 8 symbols are radially distributed symmetrically around the origin of the I, Q plane, each being deviated of said symbols substantially at 22.5 ° with respect to an axis in the I, Q plane and the series of 8 constellation symbols 8-PSK has a 3-bit bit-to-symbol mapping, so that the constellation series 8-PSK it is divided into four sub-series of two symbols each, according to the binary value expressed by the 2 least significant bits of said 3 bits; and the 2 symbols of each of these four sub-series are differentiated according to the binary value expressed by the highest significant bit of said three bits; and wherein the convolutional decoder includes a framework demapper to demap the pragmatic framework code; the improvement characterized in that the framework demapping is characterized by: a logical means (406) of demapping 8-PSK that responds to: (1) a first entry of x-bits that is applied as a first entry to it (312); wherein x is a positive integer having a given value greater than 8 to define the value of the digital input signal in phase (I); (2) a second x-bit input that is applied as a second input to it (312) to define the value of the quadrature digital input signal (Q); and (3) a 2-bit input that is applied as a third input to it (308) to select one of the four sub-series of the 8-PSK constellation series according to the binary value expressed by the input of 2 bits that apply; and in response to the first, second and third inputs thereto, the 8-PSK demapping logic means derives a 1-bit output from it that expresses the binary value of the highest significant bit of the three bits of the bit-to-bit mapping. , which is indicative of one of the two symbols of a sub-series selected from the four sub-series of the 8-PSK constellation that is closest in distance (I + Q) to the position of a symbol in that plane and , Q defined by the respective values of the digital input signal in phase (I), applied as a first input to it, and the quadrature digital input signal (Q) applied as a second input to it. 21. The convolutional decoder defined in claim 120, further characterized in that: the bit-to-symbol mapping of the 8 symbols of the constellation series 8-PSK is such that a symbol in the first quadrant of the I, Q plane substantially oriented at 22.5 ° with respect to axis I it is mapped with a binary value of 000; a symbol in the first quadrant of the I, Q plane oriented substantially at 22.5 ° with respect to the Q axis is mapped with a binary value 001; a symbol in the second quadrant of the plane I, Q oriented substantially 22.5 ° with respect to the axis I is mapped with the binary value 010; a symbol in the second quadrant I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with a binary value 011; a symbol in the third quadrant of the I, Q plane oriented substantially 22.5 ° with respect to the axis I, is mapped with a binary value 100; a symbol in the third quadrant of the I, Q plane, oriented substantially at 22.5 ° with respect to the Q axis, is mapped with the binary value 101; a symbol in the fourth quadrant I, Q, oriented substantially at 22.5 ° with respect to the axis I, is mapped with the binary value 110; and a symbol in the fourth quadrant of the plane I, Q, oriented substantially 22.5 ° with respect to the Q axis, is mapped with the binary value 111; and the 8-PSK demapping logic means includes means for deriving a binary value of "1" for the 1-bit output from it only if the product of the numerical value of the digital input signal in phase (I), multiplied by the numerical value of 1 ^ is less than the product of the numerical value of said quadrature digital input signal (Q), multiplied by the numerical value of Q2; where the numerical value of 1 ^ is 9 for sub-series 00; 4 for sub-series 01, -9 for sub-series 10 and -4 for sub-series 11; and the numerical value of Q2 is -4 for sub-series 00, -9 for sub-series 01, -4 for sub-series 10 and -9 for sub-series 11. "A TAMPER DESMAPEATOR OF A CONVOLUTIONAL DECODER" SUMMARY OF THE DESCRIPTION The framework demapping which is capable of remapping 8-PSK and QAM 16, 32, 64, 128 and 256 framework codes, comprises channel I, Q channel and remapper RAM memories, a 8-PSK logic demapping means and a multiplexer selector (MUX). Each of the RAM memory includes a look-up table that is selectively programmed for each of the QAM codes. The RAM (400) of channel I and the RAM (402) of channel Q, each of which has a storage capacity of 768 bits, directly sends its respective outputs through the MUX selector (408) as the output that it is selected from the framing demaider (406) in response to a QAM framework code that is an even power of 2 (ie, 16, 64 or 256). In response to a QAM framework code that is an odd power of 2 (that is, 32 or 128), which is selected, the respective outputs of the I channel RAM and the Q channel RAM are applied as inputs to the RAM (404) of remaper, which has a storage capacity of 320 bits and the output of the remaper RAM is sent through the MUX selector as the framing demapping output. In response to an 8-PSK fabric code being selected, the output of the 8-PSK demapping logic means is sent through the MUX selector as the framing demapping output. This configuration is structurally efficient and requires minimal storage requirements compared to a framework code debugger that employs ROM storage for QAM 16, 32, 64, 128 and 256 framework codes and 8-PSK framework codes .