KR100398969B1 - 256-qam branch methric circuit for tcm decoders - Google Patents

Abstract

A 256-QAM branch metric circuit for a TCM decoder is disclosed that consists of an I branch metric circuit portion for obtaining an I branch metric and a Q branch metric circuit having the same structure as the I branch metric circuit for obtaining a Q branch metric. The I branch metric circuitry comprises: a first adder for summing each of the 256-QAM I signal and the 256-QAM canstellation values; An absolute value unit for absolute value of each of the first through sixteenth sum values output from the first adder; A comparison selecting section for comparing the first to sixteenth absolute values from the absolute value section to select two smallest first and second minimum values; First and second registers for storing respective first and second minimum values from the comparison selector; A second adder for mutually summing first and second minimum values from the comparison selector and first and second delay values from the first and second registers; And generating a first to fourth I branch metric by selecting four signals from the seventeenth through twentieth sum values from the second adder and the first and second minimum values in response to a control signal from an external source. It consists of a multiplex section.

Description

256-AMA branch matrix circuit for TMC decoder {256-QAM BRANCH METHRIC CIRCUIT FOR TCM DECODERS}

TECHNICAL FIELD The present invention relates to a vitabi decoder, and more particularly to a 256-QAM branch metric circuit used in a vitabi decoder.

At present, the development of digital technology is accepted that digital systems have sufficient advantages in terms of spectrum and power efficiency, flexibility of service, convergence of multimedia and potential low equipment cost, both visually and audibly compared to conventional analog technology. It is getting in. Moreover, the use of cables for the distribution of video and audio signals to each individual is continually increasing and has already become a viable means for distribution.

ITU-T J.83, Digital Multi-programme systems for television, sound and data services for cable distribution, is a frequency division multiplexed cable network (e.g. cable). System structure, channel coding and modulation for digital multi-program television, sound and data signals distributed throughout the system.

ITU-T J.83 presents four appendices and recommends that cable network services use one of the systems listed in the four appendices.

ITU-T J.83 Annex B describes the frame structure, channel coding, and channel modulation for digital multiservice television distribution systems in cable systems. The specifications in Appendix B cover both 64 and 256 QAM.

In 256-QAM presented in ITU-T J.83 Annex B, it is classified into an asynchronous group of 38 data bits and a synchronization group of 30 data bits and 8 sync bits. A 38-bit string of symbols is input to a Trellis coded modulator. The 38 bits entered are assigned to the asynchronous and synchronous Trellis Group according to the group they belong to. Each trellis group forms 5QAM symbols. Of the 38 input bits forming the traris group, the two traris groups allocated by 4 bits are first coded differentially and then coded by a binary convolutional coder (BCC), respectively. . This coding outputs a total of 30 bits. Thus, the overall coding ratio for 256-QAM trellis code modulation is 19/20.

Accordingly, the present invention was created in view of the above circumstances, and an object of the present invention is to provide a branch metric circuit used for 256-QAM in a TCM decoder.

A 256-QAM branch metric circuit for a TCM decoder according to the present invention for achieving the above objects comprises: a first adder for summing each of the I-cancellation of 256-QAM and signal canstellation values in a 256-QAM map; A first absolute value unit for absolute value of each of the first through sixteenth sum values output from the first adder; A first comparison selector for comparing the first to sixteenth absolute values from the first absolute value part to select two smallest first and second minimum values among the first to sixteenth absolute values; First and second registers for storing first and second minimum values, respectively, from the first comparison selector; A second adder for mutually summing first and second minimum values from the first comparison selector and first and second delay values from the first and second registers; A second to select 17th to 20th sum values from the second adder and four signals of the first and second minimum values to generate the first to fourth I branch metrics in response to a control signal from the outside; 1 mups; A third adder for summing each of the Q signals of 256-QAM and signal canstellation values in the 256-QAM map; A second absolute value unit for absolute value of each of the eighteenth through thirty-third sum values output from the third adder; A second comparison selecting unit for comparing the seventeenth to thirty-second absolute values from the second absolute value unit to select two smallest third and fourth minimum values among the seventeenth to thirty-second absolute values; Third and fourth registers for storing third and fourth minimum values from the second comparison selector, respectively; A fourth adder for mutually summing third and fourth minimum values from the second comparison selector and third and fourth delay values from the third and fourth registers; And generating first to fourth Q branch metrics by selecting four signals from the third to fourth sum values and the third to fourth sum values from the fourth adder in response to the control signal from the outside. It is characterized by consisting of a second mux for.

1 is a diagram illustrating a 256-QAM branch metric circuit for a TCM decoder according to an embodiment of the present invention.

FIG. 2 is a detailed view of the I branch metric circuit shown in FIG. 1.

FIG. 3 is a detailed view of the Q branch metric circuit shown in FIG. 1.

<Explanation of symbols for main parts of drawing>

210, 260, 310, 360: Adder 220, 320: Absolute tooth

230, 330: comparison selection unit 240, 250, 340, 350: register

270, 370: Mutiplex part

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a diagram illustrating a 256-QAM branch metric circuit for a TCM decoder according to an embodiment of the present invention.

Referring to FIG. 1, the 256-QAM branch metric circuit 100 for a TCM decoder according to an embodiment of the present invention may include an I branch metric circuit unit 200 for obtaining an I branch metric and a Q branch metric for obtaining a Q branch metric. 300).

FIG. 2 is a detailed view of the I branch metric circuit 200 shown in FIG. 1.

Referring to FIG. 2, the I branch metric circuit 200 may include a first adder 210, a first absolute value 230, a first comparison selector 250, and first and second registers 271 and 272. ), A second subtractor 280, and a first multiplex unit 290.

The first adder 210 adds each of 256-QAM I signals and 256-QAM constellations to generate first to sixteenth sum values 2101 to 2206, and generates the first to sixth values. Sixteenth sum values 2101 to 2206 are provided to the first absolute value 230.

Preferably, the first adder 210 includes first to sixteenth adders 211 to 226 to generate the first to sixteenth sum values 2101 to 2206. Each of the first to sixteenth adders 211 to 226 generates the first to sixteenth sum values 2101 to 2206, as shown in FIG. 2. Addition values a1 to -a8 respectively.

The first absolute value unit 230 absoluteizes each of the first to sixteenth sum values 2101 to 2206 output from the first adder 210 to the first to sixteenth absolute values 2301 to 2406. And generate the first to sixteenth absolute values 2301 to 2406, respectively, to the first comparison selector 250.

Preferably, the absolute value unit 230 is configured of first to sixteenth absolute strokes 231 to 246 to generate the first to sixteenth absolute values 2301 to 2406, respectively. The first to sixteenth absolute values 231 to 246 may absoluteize the first to sixteenth sum values 2101 to 2206 from the first to sixteenth adders 211 to 226, respectively. 6 absolute values 2301 to 2406 are respectively output.

The first comparison selecting unit 250 compares the first to sixteenth absolute values 2301 to 2406 from the first absolute value unit 230, and compares the first to sixth absolute values 2301 to 2406 with each other. Select two small values and select the selected first and second minimum values 2501 and 2502 from the first and second second registers 271 and 272, the second adder 280, and the first multiplex. Each part is provided to the part 290.

Preferably, the first comparison selector 250 is composed of first to fourteenth comparison selectors 251 to 264 to generate first and second minimum values 2501 and 2502. The first comparison selector 251 compares the first absolute value and the second absolute value 2301 and 2302, selects a smaller value among the first and second absolute values 2301 and 2302, and selects the smaller value. The selected one of the first and second absolute values 2301 and 2302 is output to the ninth selector 259 as the first selection value 2511. The second comparison selector 252 compares the third absolute value 2303 from the third absolute value 233 and the fourth absolute value 2304 from the fourth absolute value 234, and A smaller value of the third and fourth absolute values 2303 and 2304 is selected, and a selected one of the third and fourth absolute values 2303 and 2304 is selected as the second selection value 2521. ) The third comparison selector 253 compares the fifth absolute value 2305 from the fifth absolute value 235 and the sixth absolute value 2306 from the sixth absolute value 236, and The tenth selector 260 selects a smaller one of the fifth and sixth absolute values 2305 and 2306 and selects the selected one of the fifth and sixth absolute values 2305 and 2306 as a third selection value 2253. Output to. The fourth comparison selector 254 compares the seventh absolute value 2307 from the seventh absolute stroke 237 and the eighth absolute value 2308 from the eighth absolute stroke 238, and The tenth selector 260 selects a smaller one of the seventh and eighth absolute values 2307 and 2308, and selects one of the seventh and eighth absolute values 2307 and 2308 as a fourth selection value 2541. Output to. The fifth comparison selector 255 compares the ninth absolute value and the tenth absolute value 2309 and 2400, selects a smaller value among the ninth and tenth absolute values 2309 and 2400, and selects the smaller value. The selected ones of the ninth and tenth absolute values 2309 and 2400 are output to the eleventh selector 261 as the fifth selection value 2551. The sixth comparison selector 256 compares the eleventh absolute value 2401 from the eleventh absolute stroke 241 and the twelfth absolute value 2402 from the twelfth absolute stroke 242, and The eleventh selector 261 is selected from the eleventh and twelfth absolute values 2401 and 2402 to select the eleventh and twelfth absolute values 2401 and 2402 as the sixth selection value 2601. ) The seventh comparison selector 257 compares the thirteenth absolute value 2403 from the thirteenth absolute stroke 243 and the fourteenth absolute value 2404 from the fourteenth absolute stroke 244, and The twelfth selector 262 selects a smaller one of the thirteenth and fourteenth absolute values 2403 and 2404, and selects one of the thirteenth and fourteenth absolute values 2403 and 2404 as a seventh selection value 2651. Output to. The eighth comparison selector 258 compares the fifteenth absolute value 2405 from the fifteenth absolute value 245 and the sixteenth absolute value 2406 from the sixteenth absolute value 246, and The twelfth selector 262 selects a smaller one of the fifteenth and sixteenth absolute values 2405 and 2406 and selects one of the fifteenth and sixteenth absolute values 2405 and 2406 as an eighth selection value 2601. Output to.

The ninth comparison selector 259 compares the first selection value 2511 from the first comparison selector 251 and the second selection value 2521 from the second comparison selector 252, and By selecting a smaller value among the first and second selection values 2511 and 2521, the selected one of the first and second selection values 2511 and 2521 is used as the ninth selection value 2591 as the ninth comparison selector ( 263). The tenth comparison selector 260 compares the third selection value 2253 from the third comparison selector 253 and the fourth selection value 2541 from the fourth comparison selector 254, and A smaller value is selected from the third and fourth selection values 2253 and 2541, and the selected one of the third and fourth selection values 2253 and 2541 is used as the tenth selection value 2591 and the thirteenth comparison selector ( 263). The eleventh comparison selector 261 compares the fifth selection value 2551 from the fifth comparison selector 255 and the sixth selection value 2561 from the sixth comparison selector 256, and By selecting the smaller one of the fifth and sixth selection values (2551 and 2561), the selected one of the fifth and sixth selection values (2551 and 2561) as the eleventh selection value (2611), the 14th comparison selector ( 264). The twelfth comparison selector 262 compares the seventh selection value 2571 from the seventh comparison selector 257 and the eighth selection value 2861 from the eighth comparison selector 258, and The smallest value of the seventh and eighth selection values 2571 and 2581 is selected, and the selected one of the seventh and eighth selection values 2257 and 2581 is used as the twelfth selection value 2612 as the twelfth selection selector ( 263). The thirteenth comparison selector 263 compares the ninth selection value 2591 from the ninth comparison selector 259 and the second selection value 2601 from the tenth comparison selector 260, and A smaller value of the ninth and tenth selection values 2591 and 2601 is selected, and the selected one of the ninth and tenth selection values 2591 and 2601 is output as the first minimum value 2501. The fourteenth comparison selector 264 compares the eleventh selection value 2611 from the eleventh comparison selector 261 and the twelfth selection value 2621 from the twelfth comparison selector 262. And selecting a smaller value among the eleventh and twelfth selection values 2611 and 2621 and outputting the selected one of the eleventh and twelfth selection values 2611 and 2621 as the second minimum value 2502.

The first register 271 stores a first minimum value 2501 from the thirteenth comparison selector 263 of the first comparison selector 250, and simultaneously stores a first previously stored minimum first value. 227 to the second subtractor 280. That is, the first register 271 outputs the first minimum value 2501 from the thirteenth comparison selector 263 by one step.

The second register 272 stores a second minimum value 2502 from the fourteenth comparison selector 264 of the first comparison selector 250, and simultaneously stores a second previously stored minimum second value. 227 is provided to the second subtractor 280. That is, the second register 272 outputs the second minimum value 2502 from the fourteenth comparison selector 264 by one step.

The second adder 280 may include first and second minimum values 2501 and 2502 from the first comparison selector 250, and first and second from the first and second registers 2710 and 272. The two delay values 2711 and 2721 are added together to generate the seventeenth to twentieth sum values 2801 to 2804.

Preferably, the second adder 280 may include the seventeenth through twentieth sum values 2811 from the first and second minimum values 2501 and 2502 and the first and second delay values 2711 and 2721. To 24), the seventeenth to twentieth summers 281 to 284. The seventeenth adder 281 mutually sums a first minimum value 2501 from the thirteenth comparison selector 263 and a first delay value 2711 from the first register 271. The eighteenth adder 282 mutually sums a second minimum value 2502 from the fourteenth comparison selector 264 and a first delay value 2711 from the first register 271. The nineteenth adder 283 mutually sums a second delay value 2721 from the second register 272 and a first minimum value 2501 from the thirteenth comparison selector 263. The twentieth adder 284 then sums together a second minimum value 2502 from the fourteenth comparison selector 264 and a second delay value 2502 from the second register 272.

In addition, the first multiplex unit 290 may include the seventeenth through twentieth sum values 2801 through 2804 and the first and second minimum values from the second adder 280 in response to a control signal from the outside. Four signals of 2501 and 2502 are selected to output the first to fourth I branch metrics i1 to i4. Preferably, the first multiplexer 290 includes a first multiplexer 291 and a second multiplexer 292. The first multiplexer 291 has a seventeenth sum value 2801 from the seventeenth adder 281 and a first minimum value 2501 from the thirteenth comparison selector 263 in response to the control signal from the outside. Outputs one as the first I branch metric i1. The second multiplexer 292 may receive an eighteenth sum value 2802 from the eighteenth adder 282 and a second minimum value 2502 from the fourteenth comparison selector 264 in response to the control signal from the outside. Outputs one as the second I branch metric i2. In addition, the first multiplex unit 290 may convert the 19th and 20th sum values 2803 and 2804 from the 19th and 20th adders 283 and 284 to the third and fourth I branch metrics i3 and i4).

Accordingly, the I branch metric circuit 200 may obtain first to fourth I branch metrics i1 to i4.

3 is a detailed view of the Q branch metric circuit 300 shown in FIG.

Referring to FIG. 3, the Q branch metric circuit 300 includes a third adder 310, a second absolute value 330, a second comparison selector 350, and third and fourth registers 371 and 372. ), A fourth subtractor 380, and a second multplex unit 390.

The first adder 210 adds each of the 256-QAM Q signals and the 256-QAM constellation to generate the 21st to 36th sum values 3101 to 3206, and generates the 21st to 21th values. 36th sum values 3101 to 3206 are provided to the second absolute value unit 330.

Preferably, the third adder 310 is configured of the 21st to 36th adders 311 to 326 to generate the 21st to 36th sum values 3101 to 3206. Each of the twenty-first to thirty-third adders 211 to 226 may generate first to sixteenth canthels to the Q value, as shown in FIG. 3 to generate the twenty-first to thirty-sixth sum values 3101 to 3206. Addition values a1 to -a8 respectively.

The second absolute value unit 330 absoluteizes each of the 21st to 36th sum values 3101 to 3206 output from the 21st adder 310 to the 17th to 32nd absolute values 3301 to 3406. Are generated respectively, and the generated seventeenth to thirty-second absolute values 3301 to 3406 are respectively provided to the second comparison selector 350.

Preferably, the second absolute portion 330 is composed of seventeenth to thirty-second absolute strokes 331 to 346 to generate the seventeenth to thirtieth absolute values 3301 to 3406, respectively. The seventeenth through thirty-second absolute strokes 331 through 346 may absoluteize the twenty-first through thirty-sixth sum values 3101 through 3206 from the twenty-first through thirty-sixth adders 311 through 326, respectively. 32 absolute values 3301 to 3406 are output, respectively.

The second comparison selector 350 compares the seventeenth to thirty-second absolute values 3301 to 3406 from the second absolute value unit 330 to the most of the seventeenth to thirty-second absolute values 3301 to 3406. Select two small values, and select the selected third and fourth minimum values 3501 and 3502 from the third and fourth second registers 371 and 372, the fourth adder 380, and the second multiplex. Each part is provided to the part 390.

Preferably, the second comparison selector 350 is comprised of fifteenth to twenty-eighth comparison selectors 351 to 364 to generate third and fourth minimum values 3501 and 3502. The fifteenth comparison selector 351 compares the seventeenth absolute value and the eighteenth absolute values 3301 and 3302, selects the smaller one of the seventeenth and eighteenth absolute values 3301 and 3302, and The selected ones of the seventeenth and eighteenth absolute values 3301 and 3302 are output to the twenty-third selector 359 as a fifteenth selection value 3511. The sixteenth comparison selector 352 compares the nineteenth absolute value 3303 from the nineteenth absolute value 333 and the twentieth absolute value 3304 from the twentieth absolute value 334, and The 24th selector 359 is selected from the 19th and 20th absolute values 3303 and 3304 to select the smaller of the 19th and 20th absolute values 2303 and 2304 as the 16th selection value 3251. ) The seventeenth comparison selector 353 compares the twenty-first absolute value 3305 from the twenty-first absolute stroke 335 and the twenty-second absolute value 3306 from the twenty-second absolute stroke 336, and The twenty-fourth selector 360 selects a smaller one of the twenty-first and twenty-second absolute values 3305 and 3306 and selects one of the twenty-first and twenty-second absolute values 3305 and 3306 as a seventeenth selection value 3531. Output to. The eighteenth comparison selector 354 compares the twenty-third absolute value 3307 from the twenty-third absolute value 337 and the twenty-fourth absolute value 3308 from the twenty-fourth absolute value 438, and The twenty-fourth selector 360 selects a smaller one of the twenty-third and twenty-fourth absolute values 3307 and 3308, and selects one of the twenty-third and twenty-fourth absolute values 3307 and 3308 as the eighteenth selection value 3551. Output to. The nineteenth comparison selector 355 compares the 25 th and 25 th absolute values 3309 and 3400 with each other, selects a smaller value among the 25 th and 26 th absolute values 3309 and 3400, and The selected ones of the 25th and 26th absolute values 3309 and 3400 are output to the 25th selector 361 as the 19th selection value 3551. The twentieth comparison selector 356 compares the twenty-seventh absolute value 3401 from the twenty-seventh absolute value 341 with the twenty-eighth absolute value 3402 from the twenty-eighth absolute value 342, and The twenty-fifth selector 361 is selected from the twenty-seventh and twenty-eighth absolute values 3401 and 3402 so that the one selected from the twenty-seventh and twenty-eighth absolute values 3401 and 3402 is selected as the twentieth selection value 3651. ) The twenty-first comparison selector 357 compares the twenty-ninth absolute value 3403 from the twenty-ninth absolute stroke 343 with the thirtieth absolute value 3404 from the thirtieth absolute stroke 344, and The twenty-sixth selector 362 selects the smaller of the twenty-ninth and thirtieth absolute values 3403 and 3404 to select the twenty-ninth and thirtieth absolute values 3403 and 3404 as the twenty-first selection value 3651. Output to. The twenty-second comparison selector 358 compares the thirty-first absolute value 3405 from the thirty-first absolute stroke 345 and the thirty-second absolute value 3406 from the thirty-second absolute stroke 346, and The twenty-sixth selector 362 selects the smaller one of the thirty-first and thirty-second absolute values 3405 and 3406, and selects one of the thirty-first and thirty-second absolute values 3405 and 3406 as the twenty-second selection value 3651. Output to.

The twenty-third comparison selector 359 compares the fifteenth selection value 3511 from the fifteenth comparison selector 351 and the sixteenth selection value 3351 from the sixteenth comparison selector 352, and By selecting a smaller one of the fifteenth and sixteenth selection values 3511 and 3521, the twenty-seventh comparison comparison selector selected as the twenty-seventh selection value 3591 is selected from the fifteenth and sixteenth selection values 3511 and 3521. 363). The twenty-fourth comparison selector 360 compares the seventeenth selection value 3531 from the seventeenth comparison selector 353 and the eighteenth selection value 3551 from the eighteenth comparison selector 354, and By selecting the smaller one of the seventeenth and eighteenth selection values 3531 and 3541, the one of the seventeenth and eighteenth selection values 3531 and 3541 is selected as the twenty-fourth selection value 3591 and the 27th comparison selector ( 363). The twenty-fifth comparison selector 361 compares the nineteenth selection value 3551 from the nineteenth comparison selector 355 and the twentieth selection value 3651 from the twentieth comparison selector 356, and The smallest value of the 19th and 20th selection values 3551 and 3561 is selected to select the 19th and 20th selection values 3551 and 3561 as the 25th selection value 361 1. 364). The twenty-sixth comparison selector 362 compares the twenty-first selection value 3701 from the twenty-first comparison selector 357 and the twenty-second selection value 3651 from the twenty-second comparison selector 358, and The smallest value of the 21st and 22nd selection values 3711 and 3581 is selected, and the 28th comparison selector (the 26th selection value 3612) is selected from the 21st and 22nd selection values 3471 and 3581. 363). The twenty-seventh comparison selector 363 compares the twenty-third selection value 3591 from the twenty-third comparison selector 359 and the twenty-fourth selection value 3601 from the twenty-fourth comparison selector 360, and A smaller value of the 23rd and 24th selection values 3591 and 3601 is selected, and the selected one of the 23rd and 24th selection values 3591 and 3601 is output as the third minimum value 3501. The 28th comparison selector 364 compares the 25th selection value 3611 from the 25th comparison selector 361 and the 26th selection value 3621 from the 26th comparison selector 362. The smallest value among the 25th and 26th selection values 3611 and 3621 is selected, and the selected one of the 25th and 26th selection values 3611 and 3621 is output as the fourth minimum value 3502.

The third register 371 stores a third minimum value 3501 from the twenty-seventh comparison selector 363 of the second comparison selector 350, and simultaneously stores a third previously stored minimum third value. As the number 3711, the fourth subtractor 380 is provided. That is, the third register 371 outputs the third minimum value 3501 from the 27th comparison selector 363 by one step.

The fourth register 372 stores the fourth minimum value 3502 from the twenty-eightth comparison selector 364 of the second comparison selector 350, and simultaneously stores a fourth previously stored minimum fourth value. It is provided to the said 4th calculating part 380 as (3721). That is, the fourth register 372 delays the fourth minimum value 3502 from the twenty-eighth comparison selector 364 by one step and outputs the fourth minimum value 3502.

The fourth adder 380 may include third and fourth minimum values 3501 and 3502 from the second comparison selector 350, and third and fourth values from the third and fourth registers 371 and 372. Fourth delay values 3711 and 3721 are added to each other to generate the 37th to 40th sum values 4801 to 4804.

Preferably, the fourth adder 380 may add the 37 th to 40 th sum values 3801 from the third and fourth minimum values 3501 and 3502 and the third and fourth delay values 3711 and 3721. To 3804), 37 to 40th summers 381 to 384. The thirty-third adder 381 mutually sums a third minimum value 3501 from the twenty-seventh comparison selector 363 and a third delay value 3711 from the third register 371. The 38th adder 382 mutually sums a fourth minimum value 3502 from the 28th comparison selector 364 and a third delay value 3711 from the third register 371. The 39th adder 383 mutually sums a fourth delay value 3721 from the fourth register 372 and a third minimum value 3501 from the 27th comparison selector 363. The 40th adder 384 adds the third minimum value 3502 from the 28th comparison selector 364 and the fourth delay value 3502 from the fourth register 372.

In addition, the second multiplier unit 390 may add the third to fourth sum values 3801 to 3804 and the third and fourth minimum values from the fourth adder 280 in response to a control signal from the outside. Four signals of the 3501 and 3502 are selected to output the first to fourth Q branch metrics q1 to q4. Preferably, the second multiplexer 390 includes a third multiplexer 391 and a fourth multiplexer 392. The third multiplexer 391 may respond to the external control signal in response to a control signal from the outside. The third multiplexer 381 and the third minimum value 3501 from the twenty-seventh comparison selector 363. Outputs one as the first Q branch metric q1. The fourth multiplexer 392 is configured to respond to a control signal from the outside so as to respond to a control signal from the outside, the 38th sum value 3802 from the 38th adder 382 and the 4th minimum value 3502 from the 28th comparison selector 364. Outputs one as the second Q branch metric q2. In addition, the second multiplex unit 390 converts the 39th and 40th sum values 3803 and 3804 from the 39th and 40th adders 383 and 384 to the third and fourth Q branch metrics q3 and q4).

Therefore, the Q branch metric circuit 300 may obtain first to fourth Q branch metrics q1 to q4.

As described above, according to the present invention, the 256-QAM branch metric circuit for the TCM decoder can be realized.

In addition, although the present invention has been described in detail with reference to the embodiments described above, the present invention is not limited thereto, and modifications and improvements are possible within the scope of ordinary knowledge of those skilled in the art.

Claims (11)

A first adder for summing each of the I-signal of 256-QAM and the signal cancellation values in the 256-QAM map; A first absolute value unit for absolute value of each of the first through sixteenth sum values output from the first adder; A first comparison selector for comparing the first to sixteenth absolute values from the first absolute value part to select two smallest first and second minimum values among the first to sixteenth absolute values; First and second registers for storing first and second minimum values, respectively, from the first comparison selector; A second adder for mutually summing first and second minimum values from the first comparison selector and first and second delay values from the first and second registers; A second to select 17th to 20th sum values from the second adder and four signals of the first and second minimum values to generate the first to fourth I branch metrics in response to a control signal from the outside; 1 mups; A third adder for summing each of the Q signals of 256-QAM and signal canstellation values in the 256-QAM map; A second absolute value unit for absolute value of each of the eighteenth through thirty-third sum values output from the third adder; A second comparison selecting unit for comparing the seventeenth to thirty-second absolute values from the second absolute value unit to select two smallest third and fourth minimum values among the seventeenth to thirty-second absolute values; Third and fourth registers for storing third and fourth minimum values from the second comparison selector, respectively; A fourth adder for mutually summing third and fourth minimum values from the second comparison selector and third and fourth delay values from the third and fourth registers; And In response to the control signal from the outside for selecting the 34 to 37 sum value from the fourth adder and four of the third and fourth minimum value to generate the first to fourth Q branch metrics 266-QAM branch metric circuit for a TCM decoder, comprising a second mux. The 256-QAM branch metric circuit for a TCM decoder according to claim 1, wherein the first adder comprises first to sixteenth adders for adding the I signal to each of the 256-QAM castellation values. . 3. The TCM decoder according to claim 2, wherein the first absolute value portion comprises first to sixteenth absolute strokes for respectively absoluteizing the first to sixteenth sums from the first to sixteenth adders. 256-QAM branch metric circuit. 4. The apparatus of claim 3, wherein the first comparison selector comprises: a first comparison selector for comparing and selecting the first absolute value and the second absolute value; A second comparison selector for comparing and selecting the third absolute value and the fourth absolute value; A third comparison selector for comparing and selecting the fifth absolute value and the sixth absolute value; A fourth comparison selector for comparatively selecting the seventh and eighth absolute values; A fifth comparison selector for comparing and selecting the ninth absolute value and the tenth absolute value; A sixth comparison selector for comparing and selecting the eleventh absolute value and the twelfth absolute value; A seventh comparison selector for comparing and selecting the thirteenth absolute value and the fourteenth absolute value; An eighth comparison selector for comparatively selecting the fifteenth absolute value and the sixteenth absolute value; A ninth comparison selector for comparing and selecting a first selection value selected by the first comparison selector and a second selection value selected by the second selector; A tenth comparison selector for comparatively selecting a third selection value selected by the third comparison selector and a fourth selection value selected by the fourth comparison selector; An eleventh comparison selector for comparatively selecting a fifth selection value selected by the fifth comparison selector and a sixth selection value selected by the sixth comparison selector; A twelfth comparison selector for comparatively selecting a seventh selection value selected by the seventh comparison selector and an eighth selection value selected by the eighth comparison selector; A thirteenth comparison selector for comparatively selecting a ninth selection value selected by the ninth comparison selector and a tenth selection value selected by the tenth comparison selector; And And a fourteenth comparison selector for comparing and selecting an eleventh selection value selected by the eleventh comparison selector and a twelfth selection value selected by the twelfth comparison selector. . 5. The apparatus of claim 4, wherein the second adder comprises: a seventeenth adder for mutually summing a first minimum value from the thirteenth comparison selector and a first delay value from the first register; An eighteenth adder for mutually summing a second minimum value from the fourteenth comparison selector and a first delay value from the first register; A nineteenth adder for mutually summing a second delay value from the second register and a first minimum value from the thirteenth comparison selector; And And a twentieth adder for summing up a second minimum value from the fourteenth comparison selector and a second delay value from the second register. 6. The first I-branch of claim 5, wherein the first multiplexer selects one of a seventeenth sum value from the seventeenth adder and a first minimum value from the thirteenth comparison selector in response to a control signal from the outside. A first multiplexer for outputting the metric; And A second multiplexer for outputting, to the second I branch metric, one of an eighteenth sum value from the eighteenth adder and a second minimum value from the fourteenth comparison selector in response to the control signal from the outside, And said first multiplexer outputs the 19th and 20th summations from said 19th and 20th adders as third and fourth I branch metrics. The 64-QAM branch metric circuit for a TCM decoder according to claim 1, wherein the third adder is comprised of twenty-first to thirty-third adders for summing the Q signal with each of the 64-QAM castellation values. . The TCM decoder according to claim 7, wherein the second absolute value unit is comprised of seventeenth to thirty-second absolute strokes for respectively absoluteizing the 21st to 36th sum values from the 21st to 36th adders. 64-QAM branch metric circuit. 9. The apparatus of claim 8, wherein the second comparison selector comprises: a fifteenth comparison selector for comparing and selecting the seventeenth absolute value and the eighteenth absolute value; A sixteenth comparison selector for comparing and selecting the nineteenth absolute value and the twentieth absolute value; A seventeenth comparison selector for comparatively selecting the twenty-first absolute value and the twenty-second absolute value; An eighteenth comparison selector for comparatively selecting the twenty-third absolute value and the twenty-fourth absolute value; A nineteenth comparison selector for comparatively selecting the twenty-fifth absolute value and the twenty-sixth absolute value; A twentieth comparison selector for comparatively selecting the twenty-seventh absolute value and the twenty-eighth absolute value; A twenty-first comparison selector for comparing and selecting the twenty-ninth absolute value and the thirtieth absolute value; A twenty-second comparison selector for comparing and selecting the thirty-first absolute value and the thirty-second absolute value; A twenty-third comparison selector for comparatively selecting a fifteenth selection value selected by the fifteenth comparison selector and a sixteenth selection value selected by the sixteenth selector; A twenty-fourth comparison selector for comparing and selecting the seventeenth selection value selected by the seventeenth comparison selector and the eighteenth selection value selected by the eighteenth comparison selector; A twenty-fifth comparison selector for comparing and selecting the nineteenth selection value selected by the nineteenth comparison selector and the twentieth selection value selected by the twentieth comparison selector; A twentysixth comparison selector for comparing and selecting the twenty-first selection value selected by the twenty-first comparison selector and the twenty-second selection value selected by the twenty-second comparison selector; A twenty-seventh comparison selector for comparatively selecting a twenty-third selection value selected by the twenty-third comparison selector and the twenty-fourth selection value selected by the twenty-fourth comparison selector; And A 256-QAM branch metric circuit for a TCM decoder comprising: a twenty-eightth comparison selector for comparing and selecting a twenty-fifth selection value selected by the twenty-fifth comparison selector and a twenty-sixth selection value selected by the twenty-sixth comparison selector . 10. The apparatus of claim 9, wherein the fourth adder comprises: a thirty seventh adder for mutually summing a third minimum value from the twenty-seventh comparison selector and a third delay value from the third register; A 38 th adder for summing up a fourth minimum value from said 28th comparison selector and a third delay value from said third register; A thirty-third adder for summing together a third delay value from the third register and a third minimum value from the twenty-seventh comparison selector; And And a 40th adder for summing up a fourth minimum value from said 28th comparison selector and a fourth delay value from said fourth register. The first Q branch of claim 10, wherein the second multiplex unit selects one of a 37 th summation value from the 37 th adder and a third minimum value from the 27 th comparison selector in response to a control signal from the outside. A third multiplexer for outputting the metric; And A fourth multiplexer for outputting one of a 38th sum value from the 38th adder and a fourth minimum value from the 28th comparison selector to the second Q branch metric in response to the control signal from the outside, And said second multiplexer outputs the 39th and 40th summations from said 39th and 40th adders as third and fourth Q branch metrics.