KR100432799B1 - 64-qam branch metric circuit for tcm decoders - Google Patents

Abstract

A 64-QAM branch metric circuit for a TCM decoder is disclosed that consists of an I branch metric circuit portion for obtaining an I branch metric and a Q branch metric circuit having the same structure as the I branch metric circuit for obtaining a Q branch metric. The I branch metric circuitry comprises: a first adder for summing each of the I-signal and 64-QAM canstellation values of 64-QAM; An absolute value unit for absolute value of each of the first through eighth sum values output from the first adder; A comparison selecting section for comparing the first to eighth absolute values from the absolute value section to select two smallest first and second minimum values; First and second registers for storing respective first and second minimum values from the comparison selector; A second adder for mutually summing first and second minimum values from the comparison selector and first and second delay values from the first and second registers; And selecting four ninth through twelve sum values from the second adder and four signals among the first and second minimum values in response to a control signal from the outside to generate the first to fourth I branch metrics. It consists of a multiplex part.

Description

64-YAM branch metric circuit for TMC decoders {64-QAM BRANCH METRIC CIRCUIT FOR TCM DECODERS}

The present invention relates to a vitabi decoder, and more particularly, to a Trellis Coded Modulator (TCM) 64-QAM branch metric circuit used in a vitabi decoder.

At present, the development of digital technology is accepted that digital systems have sufficient advantages in terms of spectrum and power efficiency, flexibility of service, convergence of multimedia and potential low equipment cost, both visually and audibly compared to conventional analog technology. It is getting in. Moreover, the use of cables for the distribution of video and audio signals to each individual is continually increasing and has already become a viable means for distribution.

ITU-T J.83, Digital Multi-programme systems for television, sound and data services for cable distribution, is a frequency division multiplexed cable network (e.g. cable). System structure, channel coding and modulation for digital multi-program television, sound and data signals distributed throughout the system.

ITU-T J.83 presents four appendices and recommends that cable network services use one of the systems listed in the four appendices.

ITU-T J.83 Annex B describes the frame structure, channel coding, and channel modulation for digital multiservice television distribution systems in cable systems. The specifications in Appendix B cover both 64 and 256 QAM.

In 64-QAM presented in ITU-T J.83 Annex B, the Trellis Coded Modulator contains a 28-bit string of four 7-bit RS symbols whose identifiers are pairs of 'A' and 'B' symbols. Is entered. The 28 bits entered are assigned to the Trellis Group. Each trellis group forms 5QAM symbols. Of the 28 input bits forming the traris group, the two traris groups assigned 4 bits are first coded differentially and then coded by a binary convolutional coder (BCC), respectively. . This coding outputs a total of 30 bits. Thus, the overall coding ratio for 64-QAM trellis code modulation is 14/15.

Accordingly, the present invention was created in view of the above circumstances, and an object of the present invention is to provide a branch metric circuit used for 64-QAM in a TCM decoder.

A 64-QAM branch metric circuit for a TCM decoder according to the present invention for achieving the above objects comprises: a first adder for summing each of the I-signal and 64-QAM castellation values of 64-QAM; A first absolute value unit for absolute value of each of the first through eighth sum values output from the first adder; A first comparison selecting unit for comparing the first to eighth absolute values from the first absolute value unit to select two first and second minimum values among the first to eighth absolute values; First and second registers for storing first and second minimum values, respectively, from the first comparison selector; A second adder for mutually summing first and second minimum values from the first comparison selector and first and second delay values from the first and second registers; A second signal for generating first to fourth I branch metrics by selecting the ninth through twelfth sum values from the second adder and four signals among the first and second minimum values in response to a control signal from an external source; 1 multiplex part; A third adder for summing each of the Q-signal and 64-QAM canstellation values of 64-QAM; A second absolute value unit for absolute value of each of the thirteenth to twentieth sum values output from the third adder; A second comparison selector for comparing the thirteenth to twentieth absolute values from the second absolute value part to select two smallest third and fourth minimum values among ninth to sixteenth absolute values; Third and fourth registers for storing third and fourth minimum values from the second comparison selector, respectively; A fourth adder for mutually summing third and fourth minimum values from the second comparison selector and third and fourth delay values from the third and fourth registers; And selecting the 21 th to 24 sum values from the fourth adder and four signals from the third and fourth minimum values in response to a control signal from the outside to generate the first to fourth Q branch metrics. And a second multiplex unit.

1 illustrates a 64-QAM branch metric circuit for a TCM decoder according to an embodiment of the present invention.

FIG. 2 is a detailed view of the I branch metric circuit shown in FIG. 1.

FIG. 3 is a detailed view of the Q branch metric circuit shown in FIG. 1.

<Explanation of symbols for main parts of drawing>

210, 260, 310, 360: Adder 220, 320: Absolute tooth

230, 330: first comparison selection unit 240, 250, 340, 350: register

270, 370: multiplex section

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 illustrates a 64-QAM branch metric circuit for a TCM decoder according to an embodiment of the present invention.

Referring to FIG. 1, the 64-QAM branch metric circuit 100 for a TCM decoder according to an embodiment of the present invention may include an I branch metric circuit unit 200 for obtaining an I branch metric and a Q branch metric for obtaining a Q branch metric. 300).

FIG. 2 is a detailed view of the I branch metric circuit 200 shown in FIG. 1.

Referring to FIG. 2, the I branch metric circuit 200 may include a first adder 210, a first absolute value 220, a first comparison selector 230, and first and second registers 240 and 250. ), A second subtractor 260, and a first multiplex unit 270.

The first adder 210 generates the first to eighth sum values 2101 to 2108 by summing each of the I-signals of 64-QAM and the 64-QAM cancellation values, and generates the first to eighth values. The sum values 2101 to 2108 are provided to the first absolute part 220.

Preferably, the first adder 210 includes first to eighth adders 211 to 218 to generate the first to eighth sum values 2101 to 2108. Each of the first to eighth adders 211 to 218 adds first to eighth canstellation values a1 to -a4 to the I value to generate the first sum value 2101.

The first absolute value unit 220 absoluteizes each of the first through eighth sum values 2101 through 2108 output from the first adder 210 to the first through eighth absolute values 2201 through 2208. And generate the first to eighth absolute values 2201 to 2208, respectively, to the first comparison selector 230.

Preferably, the absolute part 220 includes first to eighth absolute strokes 221 to 228 to generate the first to eighth absolute values 2201 to 2208, respectively. The first to eighth absolute strokes 221 to 228 may absoluteize the first to eighth sum values 2101 to 2108 from the first to eighth adders 211 to 218, respectively. 8 absolute values 2201 to 2208 are respectively output.

The first comparison selecting unit 230 compares the first to eighth absolute values 2201 to 2208 from the first absolute value unit 220 to be the most of the first to eighth absolute values 2201 to 2208. Two small values are selected and the selected first and second minimum values 2301 and 2302 are provided to the first and second second registers 240 and 250 and the second adder 260, respectively.

Preferably, the first comparison selector 230 comprises first to sixth comparison selectors 231 to 236 to generate first and second minimum values 2301 and 2302. The first comparison selector 231 compares the first absolute value and the second absolute value 2201 and 2202 with each other, selects a smaller value among the first and second absolute values 2201 and 2202, and The selected one of the first and second absolute values 2201 and 2202 is output to the fifth selector 235 as the first selection value 2311. The second comparison selector 232 compares the third absolute value 2203 from the third absolute value 223 and the fourth absolute value 2204 from the fourth absolute value 224, and The fifth selector 235 is selected from the third and fourth absolute values 2203 and 2204 to select the smaller one of the third and fourth absolute values 2203 and 2204 as the second selection value 2321. To be printed). The third comparison selector 233 compares the fifth absolute value 2205 from the fifth absolute value 225 and the sixth absolute value 2206 from the sixth absolute value 226, and The sixth selector 236 selects the smaller one of the fifth and sixth absolute values 2205 and 2206 and selects the selected one of the fifth and sixth absolute values 2205 and 2206 as a third selection value 2331. Output to. The fourth comparison selector 234 compares the fifth absolute value 2207 from the seventh absolute value 227 and the eighth absolute value 2208 from the eighth absolute value 228, and The sixth selector 236 selects a smaller one of the seventh and eighth absolute values 2207 and 2208 and selects one of the seventh and eighth absolute values 2207 and 2208 as the fourth selection value 2341. Output to. The fifth comparison selector 235 compares the first selection value 2311 from the first comparison selector 231 and the second selection value 2321 from the second comparison selector 232, and The smaller one of the first and second selection values 2311 and 2321 is selected, and the selected one of the first and second selection values 2311 and 2321 is output as the first minimum value 2301. The sixth comparison selector 236 compares the third selection value 2331 from the third comparison selector 233 and the fourth selection value 2341 from the fourth comparison selector 234, and And selecting a smaller value among the third and fourth selection values 2331 and 2341, and outputting the selected one of the third and fourth selection values 2331 and 2341 as the second minimum value 2302.

The first register 240 stores the first minimum value 2301 from the fifth comparison selector 235 of the first comparison selector 230, and simultaneously stores a first previously stored minimum first value. 2240, the second multiplier 260 is provided. That is, the first register 240 delays and outputs the first minimum value 2301 from the fifth comparison selector 235 by one step.

The second register 250 stores the second minimum value 2302 from the sixth comparison selector 236 of the first comparison selector 230, and simultaneously stores a second previously stored minimum second value. As the 2501, the second subtraction unit 260 is provided. That is, the second register 250 delays and outputs the first minimum value 2302 from the sixth comparison selector 236 by one step.

The second adder 260 may include first and second minimum values 2301 and 2302 from the first comparison selector 230, and first and second values from the first and second registers 240 and 250. The two delay values 2401 and 2501 are added together to generate ninth to twelfth combined values 2601 to 2604.

Preferably, the second adder 260 adds the ninth to twelfth sum values 2601 from the first and second minimum values 2301 and 2302 and the first and second delay values 2401 and 2501. To 2604, the ninth to twelfth summers 261 to 264. The ninth adder 261 mutually sums a first minimum value 2301 from the fifth comparison selector 235 and a first delay value 2401 from the first register 240. The tenth adder 262 mutually sums a second minimum value 2302 from the sixth comparison selector 236 and a first delay value 2401 from the first register 240. The eleventh adder 263 mutually sums a second delay value 2501 from the second register 250 and a first minimum value 2301 from the fifth comparison selector 235. The twelfth adder 266 mutually sums a second minimum value 2302 from the sixth comparison selector 236 and a second delay value 2501 from the second register 250.

In addition, the first multiplexer 270 may add the ninth to twelfth sum values 2601 to 2606 and the first and second minimum values from the second adder 260 in response to an external control signal. Four signals of 2301 and 2302 are selected to output the first to fourth I branch metrics i1 to i4. Preferably, the first multiplexer 270 includes a first multiplexer 271 and a second multiplexer 272. The first multiplexer 271 may receive a ninth sum value 2601 from the ninth adder 261 and a first minimum value 2301 from the fifth comparison selector 235 in response to the control signal from the outside. Outputs one as the first I branch metric i1. The second multiplexer 272 receives a tenth sum value 2602 from the tenth adder 262 and a second minimum value 2302 from the sixth comparison selector 235 in response to the control signal from the outside. Outputs one as the second I branch metric i2. In addition, the first multiplex unit 270 may convert the eleventh and twelfth sum values 2603 and 2604 from the eleventh and twelfth adders 263 and 264 into third and fourth I branch metrics i3 and. i4).

Accordingly, the I branch metric circuit 200 may obtain first to fourth I branch metrics i1 to i4.

3 is a detailed view of the Q branch metric circuit 300 shown in FIG.

Referring to FIG. 3, the Q branch metric circuit 300 includes a third multiplier 310, a second absolute value 320, a second comparison selector 330, and third and fourth registers 340 and 350. ), A fourth subtractor 360, and a second multiplex unit 370.

The third adder 310 generates the eleventh through eighteenth sum values 3101 through 3108 by summing each of the 64-QAM Q signals and the 64-QAM cancellation values and generating the eleventh through eighteenth sum values 3101 through 3108. 18 summed values 3101 to 3108 are provided to the second absolute part 320.

Preferably, the first adder 310 is composed of eleventh to eighteen adders 311 to 318 to generate the eleventh to eighteenth sum values 3101 to 3108. Each of the eleventh through eighteen adders 311 through 318 may include a first through eighth canstellation values a1 through -a4 to the Q value to generate the eleventh through eighteenth sum values 3101 through 3108. Add each one.

The second absolute value unit 320 generates the ninth to sixteenth absolute values 3201 to 3208 by absolute value of each of the eleventh to eighteenth sum values 3101 to 3108 output from the first adder. Each of the ninth to sixteenth absolute values 3201 to 3208 that are generated is provided to the second comparison selector 330.

Preferably, the second absolute value unit 320 is composed of ninth to sixteenth absolute strokes 321 to 328 to generate the ninth to sixteenth absolute values 3201 to 3208, respectively. The ninth to sixteenth absolute strokes 321 to 328 absoluteize the eleventh to eighteenth sum values 3101 to 3108 from the eleventh to eighteenth adders 311 to 318, respectively. 16 absolute values 3201 to 3208 are output, respectively.

The second comparison selector 330 compares the ninth to sixteenth absolute values 3201 to 3208 from the second absolute value 320 to the most of the ninth to sixteenth absolute values 3201 to 3208. Two small values are selected and the selected third and fourth minimum values 3301 and 3302 are provided to the third and fourth registers 340 and 350 and the fourth adder 360, respectively.

Preferably, the second comparison selector 330 includes seventh to twelfth comparison selectors 331 to 336 to generate the third and fourth minimum values 3301 and 3302. The seventh comparison selector 331 compares the ninth absolute value and the tenth absolute value 3201 and 3202 with each other, selects a smaller value among the ninth and tenth absolute values 3201 and 3202, and The selected ones of the ninth and tenth absolute values 3201 and 3202 are output to the eleventh selector 335 as a seventh selection value 3311. The eighth comparison selector 332 compares the eleventh absolute value 3203 from the eleventh absolute stroke 323 and the twelfth absolute value 3204 from the twelfth absolute stroke 324, and The eleventh selector 335 is selected from the eleventh and twelfth absolute values 3203 and 3204 to select the smaller one of the eleventh and twelfth absolute values 3203 and 3204 as an eighth selection value 3331. To be printed). The ninth comparison selector 333 compares the thirteenth absolute value 3205 from the thirteenth absolute value 325 and the fourteenth absolute value 3206 from the fourteenth absolute value 326, and The twelfth selector 336 selects the smaller one of the thirteenth and fourteenth absolute values 3205 and 3206 to select one of the thirteenth and fourteenth absolute values 3205 and 3206 as an eighth selection value 3331. Output to. The tenth comparison selector 334 compares the fifteenth absolute value 3207 from the fifteenth absolute value 327 and the sixteenth absolute value 3208 from the sixteenth absolute value 328, and By selecting a smaller one of the fifteenth and sixteenth absolute values 3207 and 3208, the selected one of the fifteenth and sixteenth absolute values 3207 and 3208 is used as the tenth selection value 3331 as the tenth selector 336. Output to. The eleventh comparison selector 335 compares the seventh selection value 2311 from the seventh comparison selector 331 and the eighth selection value 3331 from the eighth comparison selector 332, and The smaller value of the seventh and eighth selection values 3311 and 3321 is selected, and the selected one of the seventh and eighth selection values 3311 and 3321 is output as the third minimum value 3301. The twelfth comparison selector 336 compares the ninth selection value 3331 from the ninth comparison selector 333 and the tenth selection value 3331 from the tenth comparison selector 334. And selecting a smaller value among the ninth and tenth selection values 3331 and 3341, and outputting the selected one of the ninth and tenth selection values 3331 and 3341 as the fourth minimum value 3302.

The third register 340 stores the third minimum value 3301 from the eleventh comparison selector 335 of the second comparison selector 330, and simultaneously stores a previously stored third minimum value as a third delay value. As the 3401, the fourth subtraction unit 360 is provided. That is, the third register 340 delays and outputs the third minimum value 3301 from the eleventh comparison selector 335 by one step.

The fourth register 350 stores the fourth minimum value 3302 from the twelfth comparison selector 336 of the second comparison selector 230, and simultaneously stores the fourth previously stored minimum fourth value. As the 4501, the fourth subtraction unit 360 is provided. That is, the fourth register 350 outputs the fourth minimum value 3302 by one step from the twelfth comparison selector 336.

The fourth adder 360 may include third and fourth minimum values 3301 and 3302 from the second comparison selector 330 and third and fourth values from the third and fourth registers 340 and 450. Fourth delay values 3401 and 3501 are added to each other to generate the nineteenth to twenty-second combined values 3601 to 3604.

Preferably, the fourth adder 360 may include the nineteenth through twenty-second sum values 3601 from the third and fourth minimum values 3301 and 3302 and the third and fourth delay values 3401 and 3501. To 3604, the nineteenth to twenty-second summers 361 to 364. The nineteenth adder 361 mutually sums a third minimum value 3301 from the eleventh comparison selector 335 and a third delay value 3401 from the third register 340. The twentieth adder 362 mutually sums a fourth minimum value 3302 from the twelfth comparison selector 336 and a third delay value 3401 from the third register 340. The twenty-first adder 363 sums up a fourth delay value 3501 from the fourth register 350 and a third minimum value 3301 from the eleventh comparison selector 335. The twenty-second adder 366 mutually sums a fourth minimum value 3302 from the twelfth comparison selector 336 and a fourth delay value 3501 from the fourth register 350.

In addition, the second multiplex unit 370 may include the 19 th through 22 sum values 3601 through 3606 and the third and fourth minimum values from the fourth adder 360 in response to a control signal from the outside. Four signals from 3301 and 3302 are selected to output the first to fourth Q branch metrics q1 to q4. Preferably, the second multiplexer 370 includes a third multiplexer 371 and a fourth multiplexer 372. The third multiplexer 371 may respond to the external control signal in response to the external control signal from the nineteenth adder 361 and the third minimum value 3301 from the eleventh comparison selector 335. Outputs one as the first Q branch metric q1. The fourth multiplexer 372 responds to the control signal from the outside in response to the external control signal from the twentieth adder 362 and the fourth minimum value 3302 from the twelfth comparison selector 335. Outputs one as the second Q branch metric q2. In addition, the second multiplex unit 370 converts the 21st and 22nd sum values 3603 and 3604 from the 21st and 22nd adders 363 and 364 to the third and fourth Q branch metrics q3 and q4).

Therefore, the Q branch metric circuit 300 may obtain first to fourth Q branch metrics q1 to q4.

As described above, according to the present invention, a 64-QAM branch metric circuit for a TCM decoder can be realized.

In addition, although the present invention has been described in detail with reference to the embodiments described above, the present invention is not limited thereto, and modifications and improvements are possible within the scope of ordinary knowledge of those skilled in the art.

Claims (11)

A first adder for summing each of the I-signal of 64-QAM and the 64-QAM canstellation values; A first absolute value unit for absolute value of each of the first through eighth sum values output from the first adder; A first comparison selecting unit for comparing the first to eighth absolute values from the first absolute value unit to select two first and second minimum values among the first to eighth absolute values; First and second registers for storing first and second minimum values, respectively, from the first comparison selector; A second adder for mutually summing first and second minimum values from the first comparison selector and first and second delay values from the first and second registers; A second signal for generating first to fourth I branch metrics by selecting the ninth through twelfth sum values from the second adder and four signals among the first and second minimum values in response to a control signal from an external source; 1 multiplex part; A third adder for summing each of the Q-signal and 64-QAM canstellation values of 64-QAM; A second absolute value unit for absolute value of each of the thirteenth to twentieth sum values output from the third adder; A second comparison selector for comparing the thirteenth to twentieth absolute values from the second absolute value part to select two smallest third and fourth minimum values among ninth to sixteenth absolute values; Third and fourth registers for storing third and fourth minimum values from the second comparison selector, respectively; A fourth adder for mutually summing third and fourth minimum values from the second comparison selector and third and fourth delay values from the third and fourth registers; And A second signal for generating the first to fourth Q branch metrics by selecting the 21 to 24 sum values from the fourth adder and four signals among the third and fourth minimum values in response to a control signal from an external source; 64-QAM branch metric circuit for a TCM decoder, characterized in that it consists of two multiplex parts. The 64-QAM branch metric circuit for a TCM decoder according to claim 1, wherein the first adder comprises first to eighth adders for summing the I signal with each of the 64-QAM canstellation values. . 3. The TCM decoder according to claim 2, wherein the first absolute value unit comprises first to eighth absolute strokes for respectively absoluteizing the first to eighth sums from the first to eighth adders. 64-QAM branch metric circuit. 4. The apparatus of claim 3, wherein the first comparison selector comprises: a first comparison selector for comparing and selecting the first absolute value and the second absolute value; A second comparison selector for comparing and selecting the third absolute value and the fourth absolute value; A third comparison selector for comparing and selecting the fifth absolute value and the sixth absolute value; A fourth comparison selector for comparatively selecting the seventh and eighth absolute values; A fifth comparison selector for comparatively selecting the first selection value selected by the first comparison selector and the second selection value selected by the second selector; And A 64-QAM branch metric circuit for a TCM decoder comprising a sixth comparison selector for comparing and selecting a third selection value selected by the third comparison selector and a fourth selection value selected by the fourth comparison selector. . 5. The apparatus of claim 4, wherein the second adder comprises: a ninth adder for mutually summing a first minimum value from the fifth comparison selector and a first delay value from the first register; A tenth adder for mutually summing a second minimum value from the sixth comparison selector and a first delay value from the first register; An eleventh adder for mutually summing a second delay value from the second register and a first minimum value from the fifth comparison selector; And And a twelfth adder for summing up a second minimum value from the sixth comparison selector and a second delay value from the second register. 6. The first I-branch of claim 5, wherein the first multiplexer receives one of a ninth sum value from the ninth adder and a first minimum value from the fifth comparison selector in response to a control signal from the outside. A first multiplexer for outputting the metric; And A second multiplexer for outputting one of a tenth sum value from the tenth adder and a second minimum value from the sixth comparison selector to the second I branch metric in response to the control signal from the outside, And wherein the first multiplexer outputs the 11th and 12th sum values from the 11th and 12th adders as third and fourth I branch metrics. The 64-QAM branch metric circuit for a TCM decoder according to claim 1, wherein the third adder is comprised of thirteenth to twentieth adders for summing the Q signal with each of the 64-QAM castellation values. . 8. The TCM decoder according to claim 7, wherein the second absolute value portion is comprised of ninth to sixteenth absolute strokes for respectively absoluteizing the thirteenth to twentieth sums from the thirteenth to twentieth adders. 64-QAM branch metric circuit. 10. The apparatus of claim 8, wherein the second comparison selector comprises: a seventh comparison selector for comparing and selecting the ninth absolute value and the tenth absolute value; An eighth comparison selector for comparing and selecting the eleventh absolute value and the twelfth absolute value; A ninth comparison selector for comparing and selecting the thirteenth absolute value and the fourteenth absolute value; A tenth comparison selector for comparing and selecting the fifteenth absolute value and the sixteenth absolute value; An eleventh comparison selector for comparatively selecting a seventh selection value selected by the seventh comparison selector and an eighth selection value selected by the eighth selector; And And a twelfth selector for comparing and selecting the tenth selection value selected by the tenth comparison selector and the eleventh selection value selected by the eleventh comparison selector. The apparatus of claim 4, wherein the fourth adder comprises: a twenty-first adder configured to mutually sum a first minimum value from the eleventh comparison selector and a third delay value from the third register; A twenty-second adder for mutually summing a fourth minimum value from the twelfth comparison selector and a third delay value from the third register; A twentythird adder for summing together a third delay value from the third register and a third minimum value from the twelfth comparison selector; And And a twenty-fourth adder for summing up a fourth minimum value from the twelfth comparison selector and a fourth delay value from the fourth register. The first Q branch of claim 10, wherein the second multiplex unit selects one of a 21 st sum from the twenty-first adder and a third minimum value from the eleventh comparison selector in response to a control signal from the outside. A third multiplexer for outputting the metric; And A fourth multiplexer for outputting to the second Q branch metric one of the 22nd sum value from the 22nd adder and the 4th minimum value from the twelfth comparison selector in response to the control signal from the outside, And the second multiplex unit outputs the 23rd and 24th sum values from the 23rd and 24th adders as third and fourth Q branch metrics.