KR100495185B1 - Trellis encoded video input processing system and signal processing method in the system - Google Patents

Abstract

An adaptive trellis decoder 24 seamlessly switches between multiple input signal formats. The trellis decoder is a code sequence detection system described in the context of a Viterbi decoding system that detects codes in an input interleaved packet data signal. ). The code sequence detection system also reduces the delay (latency) between the input of encoded data and the output of decoded data. The code sequence detection system provides branch metric values in response to an input interleaved packet data signal representing one of a number of signal formats, such as a partial response format and one of normal formats. Viterbi decoder 40 decodes the packet data signal to produce a decoded output in response to branch meter values that include a substantially duplicated value associated with one of the formats. The Viterbi decoder includes a comparison circuit 43 for providing decision data in response to branch meter values associated with trellis encoded data packets. The decision data is organized by trellis state and data rulekit and is associated with trellis state transitions. Traceback network 47 provides decoded data in response to the decision data formed.

Description

Trellis-encoded video input signal processing system and signal processing method in the system

The present invention relates to the field of digital signal processing, and more particularly to a Viterbi decoder suitable for decoding signals for multi-mode trellis encoded high-definition television (HDTV).

In broadcast and communication applications, trellis coding is used to improve signal noise immunity. Trellis coding is used in conjunction with other techniques to prevent certain noise sources. One of these techniques is a data interleave technique that is used to prevent interference bursts that may occur during transmission. In this technique, data is arranged (interleaved) in a predetermined sequence before transmission, and the original sequence is restored (deinterleaved) upon reception. This operation spreads or distributes data in time in a predetermined sequence so that data loss during transmission does not result in loss of adjacent data. Instead, any data loss is distributed, making it easier to hide or correct. Another technique used to provide interference immunity is an interference suppression filtering technique that can be used to protect signals from data dependent crosstalk and cross channel interference.

Trellis coding requirements for high-definition television in the United States were established by the Advanced Television Systems Committee (ATSC) in the United States on April 12, 1995, the Digital Television Standard for HDTV Transmission. HDTV Transmissions (hereinafter referred to as the HDTV standard) are provided in sections 4.2.4-4.2.6 (Appendix D), 10.2.3.9, 10.2.3.10 and other sections. The HDTV standard provides a trellis coding system that uses an interleaving function to process 12 interleaved data streams, including 12 parallel trellis encoders at the transmitter and 12 parallel trellis decoders at the receiver. The HDTV standard trellis coding system also incorporates an interference rejection filter at the receiver decoder to reduce crosstalk and cross channel interference associated with NTSC frequencies. The interference rejection filter specified by the HDTV standard is arbitrary and may be applied to dynamically rely on the specific data to be decoded.

The use of interleaved code or dynamically selectable filter functions in conjunction with trellis decoding introduces additional trellis decoder design limitations and modes of operation. These additional design limitations and modes of operation significantly complicate the design and realization of the trellis decoding function, for example for HDTV receiver applications. In particular, trellis decoders are required to provide seamless switching between multiple modes, which may occur, for example, when switching between NTSC filtered and unfiltered input data or when switching between HDTV channels. It gets complicated. In addition, the cost and hardware limitations associated with consumer HDTV receivers require an effective cost-effective trellis decoder design. The solution of such a cost effective design would use an effective trellis decoder architecture that can accommodate interleaved data strips and multiple modes of operation.

In accordance with the principles of the present invention, the trellis decoder system comprises an adaptive trellis decoder that seamlessly switches between different signal formats. The disclosed system uses a single decoding trellis with a predetermined number of states. The trellis decoder uses a code sequence detection system that detects codes in the input interleaved packet data, as described, for example, in the context of a Viterbi decoding system. The code sequence detection system also reduces the delay (latency) between the input encoded data and the output encoded data.

A system for processing a trellis encoded video input signal representing one of a number of signal formats, such as a partial response format and one of normal formats, provides branch meter values in response to the trellis encoded video input signal. . The Viterbi decoder decodes the video input signal to produce a decoded output in response to branch meter values that include a substantially duplicated value associated with one of the formats.

According to a feature of the invention, the encoded video input signal comprises a group of interleaved trellis encoded packets. The comparison network provides decision data in response to branch meter values associated with trellis encoded data packets. Decision data is organized by trellis state and data packet and is associated with trellis state transitions. The backtracking network provides decoded data in response to the decision data formed.

1 shows a video receiver trellis decoder system 24 according to the present invention for decoding multiple interleaved data streams, such as data encoded according to the HDTV standard, for example. The system is capable of preprocessing data streams that are preprocessed in multiple formats (e.g., normal 8-level format and 15-level format that is a partial response) and preprocessed in one of multiple modes (filtered or unfiltered mode). Adaptive decoding The system also provides a seamless Viterbi decoder that switches between filtered and unfiltered data modes. Decoder 24 of FIG. 1 also uses a single adaptive trellis decoder function rather than multiple parallel trellis decoders as described in the HDTV standard.

The disclosed system is described in the context of an HDTV receiver system, but this is merely exemplary. The disclosed system may be used for other types of communication systems. The system may also be used for other types of modes of operation involving different types of preprocessing modes and functions, other types of filter functions and various interleaving methods as well as other signal noise immunity enhancement schemes.

In FIG. 1, data 1 DATA1, which is trellis-encoded input data from a demodulator (not shown), is input to the synchronization control unit 10. Data 1 is in the form of a binary data sequence of known data symbols in which each symbol is represented by an assigned digital value. A set of symbols is represented in the complex plane as a set of points called signal constellations as is known. Unit 10 detects field and segment synchronization signals in data1. The data field includes a plurality of segments, each segment containing a plurality of data packets. These synchronization signals are specified in sections 10.2.3.9-10.2.3.13 and sections 4.2.6-4.2.7 (Appendix D) by the HDTV standard. Unit 10 uses these detected signals to rearrange data 1 and provides the rearranged output data to branch meter calculator (BMC) 30 and delay unit 70. Synchronization control unit 10 also generates register reset and register enable signals R / E, which may be powered on, for example, in the event of an out-of-sync condition or in response to other inputs such as general-purpose system reset. -on), it is used to reset and synchronize the decoder 24 of FIG. The unit 10 also generates an R / E signal in response to the desynchronization signal from the synchronization monitor 80 described later. In addition, the input signal CONF is used to form the system elements of FIG. 1 to decode filtered or unfiltered data. The CONF signal indicates whether Data 1 has been prefiltered by the NTSC cross channel interference rejection filter. The CONF signal may be provided, for example, by a control processor (not shown to simplify the figure) in communication with the elements of FIG. 1, or as a discrete signal from a source indicating the presence of a filter. The use of an exclusion filter will be described in more detail with reference to FIG. 12.

The branch meter calculator 30 calculates a set of values (meter values) for each received data symbol. These meter values indicate the proximity of the received symbol to other points in the set containing symbol constellation. The calculated meter values are output to code sequence detection system 40 using a known Viterbi decoding algorithm. The code sequence detection system is described in the context of an example Viterbi decoding system implemented using an add-compare-selection (ACS) unit 43 and a backtracking control unit 47. ACS unit 43 performs a series of iterative add-compare-select operations using the meter values from unit 30 to provide a sequence of decision bits to backtrack control unit 47 and unit 30. . The decision bits output by the ACS unit 43 represent the result of the add-compare-select operation on the meter values from the unit 30. Backtracking unit 47 uses the decision bits from unit 43 to determine, for the received data symbols, the sequence of bits that are most likely to be encoded by the encoder. In addition, the input decision bits from unit 43 are used in the filtered mode to select one of the branch meter calculation signal paths within the structure of unit 30. Synchronization monitor 80 determines whether the rearranged data output from unit 10 is correctly synchronized by evaluating the meter values from one of the add-compare-select calculation units in ACS unit 43. The monitor 80 generates a desynchronization signal used by the unit 10 and other receiver elements based on the meter values evaluation.

The backtracking unit 47 outputs the trellis decoded sequence of decision bits to the trellis demapper 60 and the re-encoder 50. Unit 50 re-encodes the sequence of bits from unit 47 to provide the re-encoded bit sequence to demapper 60. In addition, the rearranged data from the unit 10 is delayed by the unit 70 and provided to the trellis demapper 60. Trellis demapper 60 uses the input data from units 47, 50, 70 to identify the transmitted data symbols and to restore the corresponding original encoded data. The recovered original data, obtained from the demapper 60, is assembled into data bytes by the assembler 90 and output to other receiver elements as needed.

The detailed operation of the trellis decoder 24 of FIG. 1 will now be described. Here, Viterbi decoding, branch meter calculations and trellis coding are known and are outlined, for example, in Digital Communication (Kluwer Academic Press, Boston, MA, USA, 1988) by Lee and Messerschmidt.

The Data1 input signal to the trellis decoder 24 is encoded according to the HDTV standard (section 4.2.5 and other sections of the appendix) using the encoding function shown in FIG. 2 shows that two input data bits X1 and X2 are encoded into three bits Z2, Z1, Z0. Each 3-bit word corresponds to one of eight symbols of R. To this end, as is known, X2 is processed by a pre-coder 102 comprising a filter component adder 100 and a register 105 to provide encoded bit Z2. X1 is encoded into two bits Z1 and Z0 by trellis encoder 103 which includes adder 115 and registers 110 and 120, as is known. The output data word from the encoder function of FIG. 2 is mapped to a sequence or symbol R of the decimal data word indicated by the mapper 125 of FIG. The encoder operation of FIG. 2 is illustrated by the attached state transition table of FIG.

The data output R from the encoder of FIG. 2 represents a symbol constellation comprising eight points or levels of four corsets. The corset values are: corset A = (A-, A +) = (-7, + 1), corset B = (B-, B +) = (-5, + 3), corset C = (C- , C +) = (-3, + 5), coset D = (D-, D +) = (-1, + 7). This mapping is arbitrary. Other mappings may be used, such as the 16 level mapping mentioned for cable operation in section 5.1 of the HDTV standard. Data encoded in this form is modulated onto the carrier and transmitted to the HDTV receiver.

In the HDTV receiver environment shown in FIG. 12, residual sideband (VSB) modulated encoded data is applied to an input processor and demodulator unit 750, which will be described later. The demodulated data is preprocessed by a preprocessor 27 including an NTSC cross channel interference rejection filter 22 and a multiplexer (MUX) 28 before being trellis decoded. In the preprocessor 27 of FIG. 12, data demodulated from the unit 750 or data filtered by the NTSC exclusion filter 22 after being demodulated from the unit 750 in response to the CONF signal is sent to the multiplexer 28. Is selected by The data selected from the multiplexer 28 is decoded by the trellis decoder 24. As is known, data that has not been pre-filtered by unit 22 prior to trellis decoding has a data format comprising eight encoded levels further modified by any noise or interference generated during the communication process. However, the data pre-filtered by the unit 22 prior to trellis decoding has a data format comprising 15 encoded levels modified by any noise or interference generated during the communication process, as is also known.

As is known, an 8 state trellis decoder is required in the filtered mode when the exclusion filter 22 is used, and a 4 state trellis decoder is required in the unfiltered mode when the filter 22 is not used. Do. Preferably, trellis decoder system 24 (FIG. 1) comprises a single eight-state trellis structure and seamlessly switches between modes. Decoder 24 provides seamless switching for optional filter modes and for data interruptions resulting from, for example, program changes and other types of transitions. Trellis decoded and intrasegment symbol deinterleaved data output by decoder 24 is provided to unit 760. The symbol deinterleaved data from the decoder is then further processed by the output processor 760 before passing through other HDTV receiver elements for processing and display, as described below.

The seamless switching capability of the trellis decoder 24 arises from the decoder structure and the design of the individual decoder elements. The main feature of the decoder 24 structure is that it includes a single eight-state ACS unit (unit 43) for filtered and unfiltered data input modes. This allows the Viterbi decoder 40 to explicitly decode the filtered or unfiltered data regardless of the state of the CONF configuration signal. We are based on the recognition that an 8 state ACS unit can be used to mimic the required 4 state ACS structure in an unfiltered mode. This is because BMC unit 30 performs parallel equivalence calculations to provide replicated branch meter values to ACS unit 43 in an unfiltered mode. The disclosed ACS architecture not only mimics the desired four-state ACS structure when duplicated input values are provided, but also allows the ACS unit 43 to operate in the same way in filtered and unfiltered modes. Another feature of the decoder 24 is that it includes an adaptive structure responsive to the input configuration signal CONF. The CONF signal indicates whether the decoder 24 input data is filtered by the NTSC exclusion filter. These features allow decoder 24 to seamlessly operate between the filtered and unfiltered modes related to the selective use of NTSC filters.

The control unit 10 detects HDTV standard compatibility field and segment synchronization signals in the input data 1. Field and segment synchronization signals are not trellis encoded or precoded. Thus, synchronization signals can be detected using known techniques described in sections 10.2, 3, 9 and 10.3.2-10.3.3.3 of the HDTV standard. These sync signals are used in unit 10 to buffer and rearrange the data contained in data 1 to provide rearranged output data segments without sync information to BMC unit 30 and delay unit 70. The data is rearranged by sequentially storing the data in buffer registers or equivalent memory, and then outputting data from the registers by omitting non-data sync packets. Non-data packets can be dropped before or after storage. The encoded, rearranged data from unit 10 is in the form of consecutive segments. Each segment contains consecutive sequential packets of twelve interleaved data streams SP1-SP12. Each packet contains one encoded data symbol defined in the HDTV standard. Both contiguous segments and contiguous packets do not include intermediate synchronization intervals. Alternative data rearrangement methods may be used. For example, instead of detecting and removing sync intervals, decoder 24 detects sync intervals and suppresses the functions of decoder 24 in a known state using reset and register enable signals for the duration of the sync intervals. Or keep it.

The control unit 10 also generates reset / enable signals R / E which are used to reset and synchronize the decoder 24. R / E signals are generated at power up and in response to a signal from the synchronization monitor 80 indicating the out of sync data state. R / E signals may also be generated in response to external input signals such as, for example, general-purpose system reset or program change indication signals. The structure of the decoder 24 allows resynchronization of the trellis decoding operation in response to the R / E signals. This resynchronization capability allows the signal trellis decoding function of the decoder 24 to provide seamless switching for selective filter mode and for data interruption, i.e. switching that the viewer is not offended.

The control unit 10 also includes another function for detecting the filtered data mode using the CONF signal and in this mode correcting for data corruption caused by the NTSC exclusion filter. Data corruption occurs in 4 symbol packets where 12 symbol intervals occur after segment synchronization. In the filtered data mode, the cross channel exclusion filter subtracts the encoded data symbols of the preceding data segment from the collocated (i.e., equality symbol packet) encoded data symbols of the current data segment. This operation yields partial response input data (sections 10.2.3.8 and 10.2.3.9 of the HDTV standard). However, when the synchronization interval (four symbols in duration) precedes four symbol packets by twelve symbol intervals, the subtraction is corrupted. This is because the synchronization value and symbol values not arranged together are subtracted from the four symbol packets. Thus, in the filtered data mode, the unit 10 identifies 12 symbols from which 4 symbol packets occur after the segment synchronization interval. In addition, unit 10 adds back the stored sync values subtracted from the exclusion filter and subtracts the stored correct symbol packet data (four co-arranged symbol packets ahead of the segment sync). In this way, unit 10 provides corrected partial response rearrangement data to units 30 and 70 in filtered data mode. Similar methods of correcting partial response data are proposed in sections 10.2.3.9 and FIG. 10.12 of the HDTV standard.

The branch meter calculator 30 calculates the values (meter values) for each encoded interleaved rearranged symbol received from the unit 10. The calculated meter values are Viterbi decoded by a unit 40 comprising an add-compare-select (ACS) unit 43 and a backtrack control unit 47. FIG. 6 shows the structure of the branch meter calculator (BMC) unit 30 of FIG. 1. FIG. 7 shows the structure of the individual BMC unit of FIG. 6 and shows each of the BMU1-BMU8 units (units 600-635). The input data provided to the S inputs of units BMU1-BMU8 in FIG. 6 include interleaved symbol data from unit 10 and inputs from ACS unit 43 (FIG. 1). Symbol data and ACS inputs (ACSI) are individually identified as inputs to units 700 and 730, respectively, in FIG.

The BMC unit of FIG. 7 sequentially processes the encoded interleaved symbol sequence from unit 10. In the unfiltered data mode selected by the CONF signal, the input symbol data of the first interleaved symbol of the data from the unit 10 is passed unchanged by the adder 700. In this mode, the multiplexer (MUX) 705 outputs a value of zero to the adder 700. The first and second distance calculators 710 and 715 calculate the Euclidean geometric distance of the encoded input symbol from the first and second corsets respectively and are two corresponding meter values outputs, the branch meter data 1 and the branch meter. Provide data 2. Table 1 defines, for example, the corset calculations performed by each BMU unit distance calculator while the BMU1 approximation for each of the corsets A and C is calculated. In addition, the first and second distance calculators 710 and 715 provide output bits C and D, respectively, through registers 740 and 735. Bits C and D indicate which of the two values in each of the first and second corsets is closest to the input symbol. Registers 740 and 735 are each serially connected to individual one-bit registers, through which bits C and D are cyclically shifted, respectively. In this way, output bits C and D for each of the 12 interleaved symbols from unit 10 (FIG. 1) are sequentially output from registers 740 and 735. The distance calculator is typically implemented using look-up tables, but may be implemented in other ways, such as calculating the distance by subtraction, absolute values, and comparison operations.

TABLE 1

In the filtered data mode of operation, input symbol data of the first interleaved symbol of data from data unit 10 is passed by adder 700 from unit 720 through multiplexers 725 and 705. It is added with the corset value W + or the corset value W-. The summed data is processed by the distance calculators 710 and 715 as described above. The corset values W + and W- belong to one of the four corsets A-D described above. The specific W + and W- corset values used for the individual BMU units are selected from the four defined corsets A-D for the particular BMU unit specified in Table 1. The W + and W− corsets are selected to recover the modified input symbol data from unit 10 into symbol data that can be processed by distance calculators 710 and 715. This operation is necessary in the filtered mode, because in the filtered mode the combination of interleave and cross-channel exclusion filtering yields the partial response input data described above, and does not yield normal symbol data calculated in the unfiltered mode ( Sections 10.2.3.8 and 10.2.3.9 of the HDTV standard). Multiplexer 730 modifies via multiplexer 725 based on the state of the ACSI input decision bits from ACS unit 43 and the state of bit input signals A and B in W + or W- adder 700. Determines whether to sum with the input data. The ACSI input decision bit from unit 43 determines which input A or input B selects between the W + and W-values that are summed by adder 700. For example, input AC is selected by the multiplexer 730 if ACSI = 1, and W + is selected by the multiplexer 725 to be added at the adder 700 via the multiplexer 730. The A and B input interconnects are shown in FIG. 6, for example A and B for unit BMU4 are provided by BMU5 and BMU6 respectively (FIG. 6). The remaining operation of the BMU unit of FIG. 7 in the filtered mode is the same as described for the unfiltered mode.

The BMC unit 30 of FIG. 1 likewise processes the remaining interleaved symbols of the rearranged data segments from the unit 10. After fully processing the rearranged data segments, BMC unit 30 repeats the above-described process beginning with the first interleaved data symbol packet of the next rearranged data segment from unit 10.

The interconnection of the same individual BMU units BMU1-BMU8 is shown in the overall BMC structure of FIG. Interleaved symbol data from unit 10 is input to the S input of units BMU1-BMU8 and processed by each of these interconnected units as described for the exemplary unit of FIG. 7. The resulting branch meter data 1 and branch meter data 2 outputs on terminals V0 and V1 of the units BMU1-BMU8 are provided to the ACS unit 43 (FIG. 1). The ACS unit 43 of FIG. 1 performs a series of iterative add-compare-select operations using branch meter data 1 and branch meter data 2 from each of the BMU units of the unit 30.

9 illustrates the interconnection between individual ACS units, including the overall ACS structure of unit 43 of FIG. 1. In FIG. 9, a single eight-state ACS structure is used for both filtered and unfiltered input modes. The ACS structure of FIG. 9 realizes the eight state transition diagram of the filtered mode of FIG. Each ACS unit (units 900-935) is associated with a trellis state (000 ... 111). The four state transition diagram of FIG. 4 shows equivalent trellis state transitions for the unfiltered mode. Rearrangement of the states shown in the state transition diagram of FIG. 5 makes the interconnection shown in FIG. 9 more apparent.

FIG. 8 shows the structure of an individual ACS unit representing each of the ACS units (units 900-935) of FIG. 9. The ACS structure of FIG. 9 sequentially processes branch meter data for individual interleaved data symbols from unit 30 (FIG. 1). Adders 805 and 810 of FIG. 8 show branch meter data 1 and branch meter data 2 obtained from other ACS units, and branch meter data 1 for interleaved-data symbols from BMU unit 30 (FIG. 1). And the branch meter data 2 are added up. The resulting two sums from units 805 and 810 are compared by unit 815. A single decision bit output indicating which of the two sums is smaller is output by the unit 815 to the register 800 and the multiplexer 820. Multiplexer 820 selects a smaller sum from the output of units 805 and 810. This selected sum appears as output path meter data at the output of register 825.

Register 800 includes twelve serially connected individual 1-bit registers through which the decision bit output from unit 815 is cyclically shifted. The decision bit output provided to the output 30 (FIG. 1) as an ACSI output is preceded by a 12 circular delay by the register 800. The decision bit output provided to the backtracking control unit 47 (FIG. 1) is preceded by a single cyclic delay by the register 800. In this way, each single decision bit output associated with each of the twelve interleaved symbols is sequentially output from register 800. Similarly, register 825 includes individual registers connected in series, through which the output path meter data from unit 820 is cyclically shifted. The bit width of the serially connected register in unit 825 is selected according to the ACS unit processing resolution requirement.

Is output path meter data from register 825 provided to / 2 other ACS units according to the interconnect diagram of FIG. For example, output path meter data from ACS unit 900 of FIG. 9 is provided to input path meter data 1, ie, V2 input, of ACS units 910 and 915. Similarly, input path meter data 1 and input path meter data 2 provided to adders 805 and 810 of FIG. 8 are provided by two different ACS units in accordance with the interconnect diagram of FIG. 9. For example, the input path meter data 1 of the ACS unit 900, that is, the V2 input is provided by the ACS unit 905, and the input path meter data 2 of the ACS unit 900, that is, the V3 input, is the ACS unit 925. Is provided by The sequence of decision bits representing the result of the add-compare-select operation sequence from the unit 30 (FIG. 1) as a beater value is obtained from the register 800 of FIG. 8, followed by a single cyclic delay. And 12 cycle delays are output to the unit 30 (FIG. 1). Each of the eight ACS units of unit 43 provides a sequence of decision bits to units 47 and 30. The eight decision bits are cyclically output from unit 43 to units 47 and 30 in parallel for each of the interleaved symbol packets provided by unit 10. The BMC unit 30 and the ACS unit 43 (FIG. 1) are interconnected as shown in Table 2. Units 30 and 43 are shown in FIGS. 6 and 9, respectively.

TABLE 2

In the unfiltered mode, there is a maximum of four distinct branch meter values for any received unfiltered symbol. In this mode, the BMC unit 30 also performs 16 parallel calculations to provide 16 branch meter values to the ACS unit 43, and a single calculation is replicated four times. Thus, the sixteen values provided to unit 43 include a replica of four distinct branch meter values. The duplication of the branch meter value input to unit 43 allows the structure of ACS unit 43 (FIG. 9) to emulate the desired four-state ACS trellis of FIG. 4. In practice, branch meter values are duplicated by the BMC unit 30, if not completely, because of system noise.

In the filtered mode, BMC unit 30 (FIG. 1) generates a maximum of 15 distinct branch meter values for each input symbol and operates according to the 8 state ACS trellis of FIG. By using the single eight-state ACS structure shown in FIG. 9 in both filtered and unfiltered modes, seamless and clear transitions of decoder 24 between modes are facilitated.

In addition, the most significant bit MSB of the output path meter data from the register 825 (FIG. 8) of one of the ACS units (units 900-935 of FIG. 9) is provided to the synchronization monitor 80 (FIG. 1). Synchronization monitor 80 counts the number of inversions in the MSB from register 825 that occur at programmed time intervals and compares the count with the programmed threshold. The programmed value may be provided by the control processor (not shown) and stored in the unit 80. If the count exceeds the threshold, a deviation signal is generated and provided to the synchronization control unit 10 (Fig. 1). Upon receiving the out of sync signal from unit 80, unit 10 provides a reset signal to unit 80 to reset the sync monitor to allow detection of another out of sync condition. The monitor 80 may alternatively be adjusted to respond to other parameters.

The structure of the ACS unit 43 provides the backtracking unit 47 (FIG. 1) with decision bit data formed by the interleaved data symbols and the ACS unit trellis state. The backtracking unit 47 has eight parallel decision bits (B1-B8, one 8 bit from the corresponding eight ACS units of the unit 43 for each encoded and interleaved symbol provided by the unit 10). Word) recursively. One 8-bit word is received cyclically per interleaved symbol. The received decision word represents eight decision bit sequences from the corresponding eight ACS units of unit 43. Unit 47 sequentially processes each decision word from unit 43 associated with the respective interleaved data symbol. The decision word is used by unit 47 to produce the most likely sequence of Z1 bits representing the interleaved symbol sequence that is de-encoded at the transmitter. Each decision bit identifies which of the two possible state transition paths leads to an ACS unit state.

FIG. 10 shows the structure of the backtracking control unit 47 (FIG. 1). The operation of the backtracking unit 47 will be described with reference to the decision word associated with the sequence of encoded and interleaved symbols output by the ACS unit 43. The structure of the traceback unit of FIG. 10 realizes the trellis decoding process shown in FIG. In step 443 following the start step 440 in FIG. 15, decision words are recursively input in the form of eight decision bit sequences from the ACS unit 43 (FIG. 1). The input decision word is provided to the forward tracking unit (FIG. 10), and is stored and delayed in the buffer memory 140 (FIG. 10) at step 445 as well. In step 450, the backtrace selection unit 145 of FIG. 10 obtains eight trellis decoded bit sequences from the decision bit sequence stored in unit 140. This trellis decoded bit sequence is a candidate for the most likely encoded Z1 bit sequence corresponding to the encoded and interleaved data symbols.

In step 450 of FIG. 15, unit 145 (FIG. 10) obtains the candidate decoded Z1 bit sequence by determining the state transition trellis path in the backtracking process. In this process, an initial preceding trellis state is identified for one of eight decision bit input sequences. This initial state is identified by using the decision bit from the ACS unit 43 (FIG. 1) of the input sequence as an indicator of the preceding transition path. From this initial predecessor state, another preceding state is identified by using a decision bit from ACS unit 43 to reverse the trellis state transition diagram until the sequence of this predecessor state is identified. From the sequence of this preceding state, a sequence corresponding to the trellis decoded bit is determined. These steps are repeated for each of the remaining sequences of decision bits stored in buffer 140 (FIG. 10). Theories regarding such backtracking processes are known and, together with other backtracking methods, are described in I.E.E.E. G. Feygin et al., "Architecture Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders" (March 1993, Vol. 41, No. 3) published in Transaction on Communication.

The described backtracking process is performed at a predetermined depth T, i.e., backtracking depth, to identify a predetermined number of preceding states. According to the known theory, the backtracking interval T is actually adopted with a backtracking interval sufficient to identify the merged, ie converged states (Lee and Messerschmidt, section 7.4.3). The converged state is a state that is likely to reach the next traceback from any initial preceding trellis state. The converged state identifies the data sequence that is most likely to be true encoded Z1 data. Thus, the merged state represents a trellis decoded data sequence to be output from the candidate sequence. In an exemplary embodiment, the backtracking process is performed in two steps, T / 2, called epochs during backtracking intervals. The selection of such epochs or subtraceback intervals is arbitrary and may be selected by the system designer.

To identify the candidate decoded trellis sequence, backtracking is performed on side by side interleaved symbol packets of consecutive, rearranged data segments. Backtracking for one of the 12 interleaved symbol packets, eg, packet 7 (SP7), is performed to identify the preceding state for the symbol data of the corresponding preceding interleaved symbol packet (here, the seventh packet SP7). ,

Although backtracking for a single trellis path is known, the disclosed system has the advantage of extending the backtracking process to include backtracking for interleaved data and for multiple candidate decision bit sequences. This extended backtracking process is performed in units of epochs using the method of FIG. 13 realized by unit 145 of FIG. In a step 645 following the start step 640 of FIG. 13, the internal storage register in the backtracking selection unit 145 is initialized at the epoch data boundary in response to a control signal from the control unit 165 (FIG. 10). do. Decision words for interleaved symbol packets, such as SP1, are cyclically input from buffer 140 (FIG. 10) at step 650. The preceding state is identified at step 655 by applying the aforementioned backtracking process using the decision bit of the decision word input of step 650, eg, B1. The main feature of the backtracking process is that the preceding state is identified for symbol data of side by side interleaved packets of consecutive data segments. For example, for the seventh interleaved symbol packet SP7 of the data segment, the corresponding seventh interleaved symbol packet decision bit is used to identify the preceding state. In step 655, trellis decoded bits corresponding to the identified preceding states of the interleaved symbols are stored in memory 150 by unit 145 (FIG. 10).

Step 660 is performed for each of the remaining decision bits (e.g., B2-B8) of the input decision word until eight trellis decoded bits for the interleaved symbols are stored in memory 150 (FIG. 10). Repeat step 655). In step 665, steps 650-660 are repeated for each of the remaining 12 interleaved symbols (e.g. SP2-SP12) of the rearranged data segments. Likewise, in step 670, steps 650-665 are repeated for a number of rearranged data segments that include epoch intervals. In step 675, the final eight candidate trellis decoded bit sequences for the interleaved input symbols are provided by the unit 145 to the memory 150. The repetition of this traceback process for one epoch interval ends at step 680 of FIG. 13 and completes step 450, which is the process included in FIG.

In steps 460 and 465 of FIG. 15, forward tracking unit 160 (FIG. 10) identifies a trellis decoded bit sequence that is most likely to correspond to the sequence encoded among the eight candidate sequences and transmitted to the receiver. . In step 470, the last identified trellis decoded sequence following the delay is passed through the multiplexer 155 by the memory 150 in response to the selection signal from the tracking unit 160 through the trellis demapper ( demapper 60 and re-encoder 50 (FIG. 1).

In steps 460 and 465 of FIG. 15, the tracking unit 160 identifies the trellis decoded bit sequence and convergence state that is most likely to correspond to the transmitted interleaved symbol packet sequence. The traceback process shown in FIG. 14 is used to identify the trellis decoded bit sequence in the epoch on a per-epoch basis. Forward tracking techniques are a cost effective way to reduce data decoding delay (latency).

In step 460 of Fig. 15, for each of the eight data sequences, the forward tracking process of Fig. 14 is performed during the epoch interval of the input data to update two pointers, namely pointer 1 and pointer 2. These pointers are used to identify trellis decoded bit sequences.

In step 843 following the starting step 840 in FIG. 14, eight pointer2 indicators are updated with corresponding pointer1 indicator values. These pointers are stored in unit 160. In step 845, an internal storage register in unit 160 is initialized at the epoch data boundary in response to a control signal from control unit 165 (FIG. 10). Control unit 165 synchronizes tracking units 145 and 160 to begin tracking at the epoch boundary by providing a control signal in response to the R / E input signal from unit 10 (FIG. 1). Non-delayed decision words for interleaved symbol packets, such as SP1, are cyclically input from ACS unit 43 (FIG. 1) at step 850.

In step 855, a three step process is used to update one of the eight distinct Pointer1 indicators associated with the eight data sequences of the input decision word. Decision bits of the undelayed input, for example B1, are used to identify the preceding state from the current state by applying the aforementioned backtracking process. The preceding state is identified for symbol packet data of side by side interleaved symbol packets (eg SP1) of the preceding data segment described for the backtracking process of unit 145. The identified preceding state is used to select one of eight distinct Pointer1 indicators associated with the eight data sequences of the input decision word. The state indicated by the selected pointer 1 of the interleaved symbol (eg SP1) is stored in the pointer 1 indicator associated with the sequence of decision bits (eg, the sequence for B1) that overlaps the contents of any preceding pointer 1.

Step 860 is followed by step 855 for each of the remaining decision bits (bits B2-B8 in this example) of the input decision word until each of the eight data sequences for the interleaved symbol SP1 is stored in unit 160. Repeat). In step 865, steps 850-860 are repeated for the remaining interleaved symbols (symbols SP2-SP12 in this example) of the twelve symbol rearranged data segments. Likewise, step 870 repeats steps 850-865 until a number of rearranged data segments including epoch intervals T / 2 have been processed. This iteration of the forward tracking process ends at step 880 of FIG. 14 and completes step 460, which is the process included in FIG.

In step 465 of Fig. 15, the updated pointers, pointer1 and pointer2, are used to identify the converged state. In normal operation, pointers 1 and 2 for a particular data sequence following the backtracking interval T represent a preceding state that occurs before one epoch. Pointer 1 is the current epoch pointer and pointer 2 is the previous epoch pointer. Pointers 1 and 2 represent one traceback interval T for the preceding state converged together. In the absence of an error, pointers 1 and 2 for all eight data sequences represent the same convergence state, thus identifying the same data sequence emitted from memory 150. One of the pointer1 indicators for the eight data sequences is selected and used to identify one of the eight pointer2 indicators. This identified pointer 2 indicator is then used to identify the convergence state. Thus, one of the eight pointer 1 indicators is used for identification together with one of the eight pointer 2 indicators. However, pointers may be averaged or selected on a number of different criteria to improve reliability in converged state selection.

The converged state determined in step 465 is used to indicate which of the eight candidate trellis decoded bit sequences in step 470 should be emitted from the memory 150 through the multiplexer 155 (FIG. 10). do. The selected decoded data sequence is the data that is most likely to correspond to the transmitted encoded interleaved symbol sequence.

The final identified trellis decoded sequence following the delay is trellis demapper 60 via the multiplexer 155 (FIG. 10) by the memory 150 in response to the selection signal from the tracking unit 160. And to the re-encoder 50. The emitted trellis decoded sequence output from multiplexer 155 to trellis demapper 60 and re-encoder 50 (FIG. 1) is the X1 bit of the interleaved symbol encoded by the encoder of FIG. Play the original sequence. The X1 bit sequence is the same as the Z1 bit sequence shown in FIG. The steps of the process of Figure 15 are repeated as long as the input decision data is available. If no input decision data is available, the process ends at step 480.

Unit 50 (FIG. 1) sequentially encodes the interleaved Zl sequence of bits from unit 47 (and multiplexer 155 of FIG. 10) and re-encodes Z0 bit sequence to demapper 60. To provide. The re-encoding function used to calculate Z0 from Z1 mimics the equivalent function performed at the encoder prior to transmission shown in FIG. In addition, the rearranged interleaved symbol data from unit 10 is delayed by unit 70 and synchronized to the output of unit 47 and provided to trellis demapper 60.

11 shows the structure of the trellis demapper 60 (FIG. 1). The trellis demapper 60 sequentially processes the synchronized and interleaved data sequences from units 47, 50, 70 (FIG. 1). In the unfiltered data mode selected by the CONF signal, delayed input symbol data of the first interleaved symbol from unit 70 passes through the adder 950 of the demapper of FIG. 11 unchanged. In this mode, the multiplexer 955 outputs a value of zero.

Re-encoded input data Z1 and Z0 from units 50 and 70 for the first interleaved symbol define only one of the four corsets described above, as indicated in symbol mapper table 125 of FIG. . For example, Z1 = 1, Z0 = 0 defines the coset point C (-3, +5). The lookup table function 960 of FIG. 11 compares the input symbols output from the adder 950 with each of the two constellation points of the corset defined by inputs Z1 and Z0. The constellation point closest to the received delayed symbol point is determined, and the Z2 value of this constellation point is provided to post-coder 997 as the decoded Z2 value for the first interleaved symbol. Post coder 997 provides an inverse function of precoder 102 of FIG. 2 using adder 980 and register 975, and decodes the Z2 value to provide the X2 bits for the first interleaved symbol. Demapper 60 repeats this process for each interleaved symbol packet received from unit 70 using the synchronized relevant symbol data from units 47 and 50. In this way, a sequence of X2 bits for the interleaved symbols from unit 70 (FIG. 1) corresponding to the interleaved symbols input to decoder 24 are sequentially output from adder 980.

In the filtered data mode, the modified and delayed symbol packet data for the first interleaved symbol from unit 70 (FIG. 1), in adder 950 of FIG. 11, from multiplexer 955 and unit 995 from unit 985. And one of the eight constellation values provided through 970). The constellation value selected from the unit 985 is selected to recover the symbol data input to the adder 950 into symbol data that can be processed by the unit 960. This operation is necessary because, as described above, in the filtered mode, the combination of interleaving and rejection filtering produces partial response input data (section 10.2.3.9 of the HDTV standard). Multiplexer 970, via multiplexer 955, is based on the state of Z0 and Z1 data delayed by register 965 and Z2 output from function 960 delayed by register 965. Select the migration point (A -... D +). The remaining filtered mode operation of the demapper 60 is the same as described for the unfiltered mode.

Demapper 60 (FIG. 1) provides assembler 90 with recovered X2 data along with the synchronized X1 data. The X1 and X2 bits corresponding to each interleaved data symbol input to decoder 24 are sequentially provided to assembler 90 by unit 60. Each X1 and X2 bit pair is trellis decoded data for a symbol packet. Assembler 90 assembles four X1, X2 bit pairs for side by side interleaved packets of consecutive data segments into one 8-bit byte. Unit 90 thus assembles a data byte for each of the 12 interleaved data packets. The unit outputs the bytes in bytes for each of the 12 interleaved symbol packet strings. In this way, unit 90 provides the intrasegment symbol deinterleaved output data for use by the remaining receiver elements.

In the example HDTV receiver system partially shown in FIG. 12, the encoded data is processed and demodulated by processor and demodulator 750. Unit 750 includes an input channel tuner, an RF amplifier, an IF (intermediate frequency) amplifier, and a mixer stage to down modulate the modulated signal to a lower frequency band suitable for further processing. Input processor 750 also includes an automatic gain control network, an analog-to-digital converter, and a timing and carrier recovery network. The received signal is demodulated as basis by a carrier recovery network in unit 750. The carrier recovery network may include, as is known, an equalizer, rotator, slicer, phase error detection network, as well as a phase controller that controls the equalizer and rotator operation.

According to the invention, one of the demodulated data and the demodulated data processed by the NTSC exclusion filter 22 is selected by the multiplexer in response to the CONF signal and decoded by the decoder 24. The trellis decoded and intrasegment symbol deinterleaved data output by decoder 24 is provided to unit 760. The symbol deinterleaved data from decoder 24 is convolutionally deinterleaved and Reed-Solomon decoded by output processor 760 before being passed to another HDTV receiver element for other processing and display. Intrasegment deinterleave processing associated with trellis coding is another process that is distinct from intersegment deinterleaving processing (sections 10.2.3.9 and 10 2.3.10 of the HDTV standard). For example, the above mentioned Lee and Messerschmidt materials describe the functions discussed in connection with units 750 and 760.

The structure described with reference to FIGS. 1 to 15 is not exclusive. Other structures may be derived which achieve the same object according to the principles of the invention. For example, a single trellis decoder may be used to decode N packets of input data, and one or more trellis decoders (eg, less than N) may be used, depending on the system. Also, structures with other numbers of trellis transition states may be created. The principle of the present invention is not limited to the eight-state structure described above. In addition, the functionality of elements of various structures may be implemented by some or all of the programmed instructions of the microprocessor.

FIELD OF THE INVENTION The present invention relates to the field of digital signal processing, and more particularly to providing a Viterbi decoder suitable for decoding signals for multi-mode trellis encoded high definition television (HDTV).

1 is a diagram of a trellis decoder system in accordance with the present invention for decoding interleaved multiple data streams and providing seamless switching between multiple modes of operation;

FIG. 2 is a diagram of a trellis encoder, pre-coder and symbol mapper, described in the HDTV standard. FIG.

3 is an encoder status table derived for the encoder system of FIG.

4 is a diagram of four-state trellis derived for trellis decoded data that has not been pre-filtered by an NTSC co-channel rejection filter.

5 is a diagram of an eight-state trellis derived for trellis decoded data that is not pre-filtered by an NTSC exclusion filter.

FIG. 6 is a block diagram illustrating a branch metric computer structure suitable for the trellis decoder of FIG.

FIG. 7 illustrates a quarter meter calculation unit architecture suitable for the branch meter calculator architecture of FIG.

8 shows the structure of an individual Add-Compare-Select (ACS) unit according to the invention, suitable for the ACS function structure of FIG.

9 illustrates an ACS functional architecture, in accordance with the present invention, suitable for the trellis decoder of FIG.

10 shows a traceback control unit architecture according to the invention, suitable for the trellis decoder of FIG.

FIG. 11 illustrates a trellis demapper architecture suitable for the trellis decoder of FIG.

12 is a diagram of a seamless switchable trellis decoder that adaptively decodes an interleaved multiple data stream of filtered or unfiltered data in the context of an HDTV receiver system.

13 is a flowchart of a process for performing a trellis backtracking function used for trellis decoding of interleaved data, in accordance with the present invention;

14 is a flowchart of a forward tracking process used for trellis decoding of interleaved data, in accordance with the present invention.

FIG. 15 is a diagram of a trellis decoding process incorporating the process of FIGS. 13 and 14 implementing the traceback control function of FIG. 10, in accordance with the present invention;

      ※ Explanation of code about main part of drawing ※

24: Trellis Decoder 27: Preprocessor

30: Quarter Meter Calculator 40: Viterbi Decoder

43: addition-compare-selection unit

Claims (12)

A system for processing trellis encoded video input signals representing one of a number of signal formats, Means 30 for providing branch metric values in response to the trellis encoded video signal, the branch meter values comprising a substantially duplicated value associated with one of the formats. Means (30) for providing the branch meter value; One Viterbi decoder (40) for decoding the video input signal to produce a decoded output in response to the branch meter value including the duplicated value; And a symbol processor (60) responsive to the decoded output. 2. The system of claim 1, wherein the branch meter values comprise different numbers of substantially replicated branch meter values for different formats. The system according to claim 1, wherein said providing means is a quarter meter calculator. 2. The apparatus of claim 1, wherein the trellis encoded video signal comprises groups of interleaved trellis encoded data packets, And said providing means sequentially processes said data packets to provide corresponding sequential branch meter values. 5. The system of claim 4, further comprising a symbol packet deinterleaver for deinterleaving the decoded output. 2. The system of claim 1, wherein the decoder comprises a comparison network for comparing the branch meter values to provide a decision representative output. 7. The system of claim 6, wherein the decoder further comprises a backtracking network responsive to the decision indication output to provide the decoded output. 2. The apparatus of claim 1, wherein the trellis encoded video signal comprises groups of trellis encoded data packets; And the symbol processor identifies symbol codes associated with the data packets. 2. The comparison network of claim 1, wherein the comparison data for providing decision data associated with trellis state transitions in response to the branch meter values, wherein the decision data is organized by trellis state and a data packet. Further comprising a network; And the Viterbi decoder generates the decoded output in response to the constructed decision data. 10. The system of claim 9, wherein said decision data is organized in series by said data packet. 11. The system of claim 10, wherein said decision data is organized in parallel by said trellis state. A method for use in a system for processing trellis encoded video input signals representing one of a plurality of signal formats, the method comprising: Forming branch meter values in response to the trellis encoded video signal, wherein the branch meter values associated with one of the formats comprise a substantially duplicated value. Step 30, and And (40) Viterbi decoding the video input signal in response to the branch meter values comprising the duplicated value.

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