GB2332835A - Differential post-coder for a tcm decoder - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/256—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2933—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code
- H03M13/2936—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using a block and a convolutional code comprising an outer Reed-Solomon code and an inner convolutional code
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
- H04L27/3416—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes
- H04L27/3427—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
Abstract
A trellis-coded modulation (tcm) decoder has a differential post-coder 37-3 for correcting phase errors using fewer processing steps 41-49 than the prior art (figure 3). A pair of current input signals Xi, Yi are delayed by one bit 41, 42 to form previous input signals which are inputted together with inverted forms 43,44 to a first selector 48. An output signal Wj is selected from these inputs based on the current input signals. On the basis of an exclusive-OR (XOR) of the current input signals 46, a second selector 49 chooses between an exclusive-OR 47 of the delayed input signals and an inverted version of this 45 to provide a second output signal Zj. A second embodiment using the same number of processing steps is disclosed (figure 5). The tcm decoder is applicable to digital cable television systems using quadrature amplitude modulation (QAM).
Description
POST-CODING METHOD AND APPARATUS FOR USE IN A TCM DECODER
The present invention relates to a trellis coded modulation (TCM) decoder in a digital cable television system, and, more particularly, to a differential post-coder for use in a TCM decoder.
Recently, there has been increasing interest in a certain type of combined modulation and coding scheme, called trelliscoded modulation (TCM), that can achieve a coding gain without any bandwidth expansion in a bandwidth-limited channel. The
TCM involves the use of a finite-state encoder and a nonbinary modulator. Therefore, as compared with a conventional modulation, the TCM can achieve net coding gains of 3 to 6 dB over an uncoded case, in the presence of an additive white
Gaussian noise (AWGN).
In a process implementing a concatenated coding by connecting two different coders, e. g., an inner and an outer coders, to enhance data reliability, either a well known convolutional encoder or a TCM encoder is used as the inner coder and data encoded by the inner coder is decoded by a trellis decoder employing a Viterbi algorithm, while a Reed
Solomon coder can be used as the outer coder. The outer coder corrects errors which have not been remedied at the inner coder to thereby minimize the rate of errors. This concatenated coding technique achieves more advanced implementation with a much less complex hardware than a coding technique having only one coding process.
Referring to Fig. 1, there is shown a schematic block diagram of cable transmission processing in a conventional digital cable television system, wherein the system comprises a transmitter including a motion picture expert group (MPEG) framing block 21, a forward error correction (FEC) encoder 22, a quadrature amplitude modulation (QAM) modulator 23 ; a channel 24 ; and a receiver including a QAM demodulator 25, a
FEC decoder 26 and an MPEG framing block 27.
The MPEG framing block 21 receives an MPEG-2 transport data stream consisting of continuous stream of fixed length 188 byte packets and delivers MPEG packet synchronize to the receiver. For carriage of transport protocols, e. g., asynchronous transfer mode (ATM), other than the MPEG-2 Transport, the. IPEG framing block 21 can be bypassed. The
FEC encoder 22 uses various types of error correcting algorithm and interleaving techniques such as Reed-Solomon coding, interleaving, randomization and trellis coding and the
QAM modulator 23 uses 64-ary QAM or 256-ary QAM. The receiver performs operations of the transmitter in the reverse order.
The FEC encoder 22 includes a Reed-Solomon encoder 22-1, an interleaver 22-2, a randomizer 22-3 and a trellis encoder 22-4 ; and the FEC decoder 26 includes a trellis decoder 26-1, a derandomizer 26-2, a deinterleaver 26-3 and a Reed-Solomon decoder 26-4.
The Reed-Solomon encoder 22-1 performs Reed-Solomon encoding by using a (128, 122) Reed-Solomon code which is capable of correcting up to three symbol errors per Reed
Solomon block. The interleaver 22-2 evenly disperses the symbols in order to protect them against a burst of symbol errors. The randomizer 22-3 randomizes the interleaved data to allow the QAM demodulator 25 to synchronize effectively.
The trellis encoder 22-4 employs a convolutional encoding technique.
Referring to Fig. 2A, there is shown a schematic block diagram of the trellis encoder 22-4 for a 64-ary QAM, which has a data formatter 31, a coding processor 33 and a QAM mapper 34 (see ITU-T Recommendation J. 83, Digital Multi
Programme Systems for Television Sound and Data Services for
Cable Distribution, Television and Sound Transmission, International Telecommunication Union-Telecommunication Standardization sector, October 1995).
The data formatter 31 receives a sequence of 28 bit data stream, i. e., of four 7 bit Reed-Solomon symbols, which are labeled in a pair of'A1'and'A2'groups and another pair of 'B1'and'B2'groups, from the randomizer 22-3, wherein'A1' group reads'A1, A2, A4, A5, A7, A8 and A10'from least significant bit (LSB) to most significant bit (MSB) ;'A2' group reads'All, A12, A13, AO, A3, A6 and A9'from LSB to
MSB ;'B1'group reads'B1, B2, B4, B5, B7, B8, B10'from LSB to MSB ; and'B2'group reads'B11, B12, B13, B0, B3, B6 and B9'from LSB to MSB. The four MSB's'AO, A3, A6 and A9'of the'A2'group are provided to the coding processor 33 by one bit at a time from LSB to MSB ; and the remaining 3 bits of the 'A2'group and all the 7 bits of the'A1'group are directly provided to the QAM mapper 34 by two bits at a time from LSB to MSB. The same process is carried out for the pair of the 'B1'and the'B2'groups. A total of 20 bits, four bits at a time, are transferred from the data formatter 31 to the QAM mapper 34 without any encoding scheme.
In the meantime, the coding processor 33, which contains a differential pre-coder 33-1 and two binary convolutional coders (BCC's) 33-2 and 33-3, performs both a differential encoding and a convolutional encoding for two set of four MSB's, i. e.,'A0, A3, A6 and A9'of the'A2'group and'B0, B3, B6 and B9'of the'B2'group, to provide two sets of five coe bits, i. e''T1 U2, U3, U4 and US'and'VI, V2, V3, V4 and V5'to the QAM mapper 34. The differential pre-coder 33-1 performs a 90 degree rotationally invariant trellis coding in order to correct phase errors.
The QAM mapper 34 receives the uncoded 4 bits, i. e.,'C1, C2, C4 and C5', from the data formatter 31 and the coded 2 bits, i. e.,'CO and C3', from the two binary convolutional coders 33-2 and 33-3 of the coding processor 33 at a time ; and provides the 6-bit constellation symbol, i. e., 64-ary QAM constellation symbol to the QAM modulator 23.
Another TCM encoder (not shown) of a 256-ary QAM receives a sequence of 38 bit data stream ; performs a differential encoding and a convolutional encoding for two sets of four
MSB's, i. e,'A0, A4, A8 and A12'and'B0, B4, B8 and B12'to generate two sets of five coded bits, i. e.,'U1, U2, U3, U4 and U5'and'V1, V2, V3, V4 and V5' ; outputs 256-ary QAM constellation symbol based on the two sets of five coded bits and the remaining six sets of 5 uncoded bits.
Referring to Fig. 2B, there is shown a schematic block diagram for the trellis decoder 26-1 of a 64-ary QAM, which has a QAM demapper 35, a coding processor 37 and a data deformatter 38.
The QAM demapper 35 receives the 64-ary QAM constellation symbol from the QAM demodulator 25 and provides 6 bits of CO to C5 at a time by using a QAM demapping. The coding processor 37, which contains two binary convolutional decoders 'RbD's) 37-1 and 37-2 and a differential post-codr 37-3, performs a trellis decoding and a differential decoding for two sets of five bits'U1, U2, U3, U4 and U5'and'V1, V2, V3, V4 and V5'fed from two output terminals CO and C3 of the QAM demapper 35 to provide two sets of four decoded symbols'AO, A3, A6 and A9'and'B0, B3, B6 and B9'to the data deformatter 38, wherein each of the two BCD's 37-1 and 37-2 and the differential post-coder 37-3 correspond to each of the two binary convolutional encoders 33-2 and 33-3 and the differential pre-coder 33-1. A total of 20 bits, four bits at a time, are directly transferred from the QAM demapper 35 to the data deformatter 38.
In the meantime, the differential pre-coding equations for the differential pre-coder 33-1 shown in Fig. 2A are described as follows :
wherein W and Z. represent two current input signals of the differential pre-coder, X and Yj represent two current output signals of the differential pre-coder and X, and Y represent two previous output signals of the differential precoder (see ITU-T recommendation J. 83, October 1995, p 23).
Therefore, The differential post-coding equations for the differential post-coder 37-3 shown Fig. 2B can be calculated according to Eq. 1 as follows :
wherein Xi and Yj represent two current input signals of the differential post-coder, X, and Yj1 represent two previous input signals of the differential post-coder and Wj and Z represent two current output signals of the differential postcoder.
Referring to Fig. 3, there is shown a block diagram of the conventional differential post-coder 37-3 in accordance with Eq. 2.
Among each pair of input signals Xj and Yj, which may be treated as a pair of current input signals, a first current input signal Xj is provided to a first delay 131 and a first and a third exclusive-OR (XOR) gates 133 and 135 ; and a second, i. e., the other, current input signal Yj is provided to a second delay 132 and the first exclusive-OR gate 133.
At the first delay 131, the first current input signal X is delayed by one bit so that a delayed input signal is provided as a first previous input signal Xj1 to a second and the third exclusive-OR gates 134 and 135 ; and, at the second delay 132, the second current input signal Yj is delayed by one bit so that a delayed input signal is provided as a second previous input signal Yj1 to the second exclusive-OR gate 134.
At the first exclusive-OR gate 133, the two current input signals X and Y. are exclusive-ORed so that Xj#Yj is provided to a fourth exclusive-OR gate 136 ; at the second exclusive-OR gate 134, the two previous input signals Xj1 and Yj1 are exclusive-ORed so that Xj-1#Yj-1 is provided to the fourth exclusive-OR gate 136 and a AND gate 137 ; at the third exclusive-OR gate 135, the first current and the first previous input signals Xj and X. are exclusive-ORed so that Xj@Xj1 is provided to a fifth exclusive-OR gate 138 ; and, at the fourth exclusive-OR gate 136, Xi and Xj-1#Yj-1 are exclusive-ORed so that Xj#Yj#Xj-1#Yj-1 is provided to the AND gate 137 and outputted as a second output Zj to the data deformatter 38 shown in Fig. 2B.
In the meantime, at the AND gate 137, Xj-1#Yj-1 and Xj#Yj# Xj Yj1 are logically multiplied with each other so that (Xj-1#Yj-1 (Xj#Yj#Xj-1#Yj-1) is provided to the fifth exclusive-OR gate 138 ; and, at the fifth exclusive-OR gate 138, X and (Xj-1#Yj-1) (Xj#Yj#Xj-1#Yj-1) are exclusive-ORed so that Xjexj-ie (Xj-1#Yj-1) (Xj#Yj#Xj-1#Yj-1) is provided as a first output signal W to the data deformatter 38 shown in Fig. 2B.
Since, however, three exclusive-OR gates and one AND gate should be operated successively in order to calculate the first output signal Wj, the differential post-coding is delayed and the circuit is unnecessarily complicated.
It is, therefore, an object of the present invention to provide a post-coding method and apparatus for use in a TCM decoder with smallest calculation steps.
According to the present invention, there is provided a post-coding method for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder includes a differential post-coder and two binary convolutional decoders
and the differential post-coder converts a pair of current input signals X and Yj to a pair of output signals W and Zj in which phase errors are corrected, the method comprising the steps of :
(a) delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals X and Yj-1 ;
(b) inverting the two previous input signals X. and Yj-1, respectively, to generate two inverted previous input signals -Xj-i and #Yj-1 ;
(c) exclusive-ORing the two previous input signals X and Yj-1 to generate a previous exclusive-ORed signal Xj-1#Yj-1 ;
(d) inverting the previous exclusive-ORed signal Xj-1#Yj-1 to generate an inverted previous exclusive-ORed signal - (Xj-1#Yj-1) ;
(e) selecting one of the two previous input signals Xj-1 and Yj1 and the two inverted previous input signals #Xj-1 and #Yj-1 as a first output signal Wj based on the two current input signals Xj and Yj ; and (f) choosing one of the previous exclusive-ORed signal Xj-1#Yj-1 and the inverted previous exclusive-ORed signal - as a second output signal Z. based on the two current input signals X and Yj.
According to the present invention there is also provided
a post-coding apparatus for use in a trellis-coded
modulation (TCM) decoder, wherein the TCM decoder is equipped
with the post-coding apparatus itself and two binary
convolutional decoders and the apparatus converts a pair of
current input signals Xj and Yj to a pair of output signals W. and Z. in which phase errors are corrected, the apparatus
comprising :
two delaying means for delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals X. and Y,-J ;
two inverters for inverting the two previous input signals Xj-1 and Yj-1, respectively, to generate two inverted previous input signals #Xj-1 and #Yj-1; an exclusive-OR gates for exclusive-ORing the two previous input signals Xj-1 and Yj-1 to generate a previous exclusive-ORed signal Xj-1#Yj-1; an inverter for inverting the previous exclusive-OReS signal j-1 to generate an inverted previous exclusive-ORed signal # (Xj-1#Yj-1); a selector for selecting one of the two previous input signals Xjl and Yj1 and the two inverted previous input signals-Xj1 and-Yj1 as a first output signal W based on the two current input signals Xj and Yj ; and
a chooser for choosing one of'ne previous exclusive-ORed signalX,@Y.andtheinverted previous exclusive-ORed signal - (Xj-1#Yj-1) as a second output signal Z. based on the two current input signals Xj and
According to the present invention there is also provided
a post-coding method for use in a trellis-coded
modulation (TCM) decoder, wherein the TCM decoder includes a
differential post-coder and two binary convolutional decoders
and the differential post-coder converts a pair of current
input signals Xj and Yj to a pair of output signals W. and Z. in which phase errors are corrected, the method comprising the
steps of :
(a) delaying two current input signals Xj and Y by one
bit, respectively, to generate two previous input signals X. and Yj-1 ;
(b) inverting the two current input sigrals Xj and Yj, 3 respectively, to generate two inverted current input signals
-Xj and-Yj ; (c) exclusive-ORing the two current input signals Xj and Yj to generate a previous exclusive-ORed signal Xj@Yj ;
(d) inverting the current exclusive-ORed signal Xj#Yj to
generate an inverted previous exclusive-ORed signhals # (Xj#Yj) ; te) selecting one of the two current input signals Xj and Y. and the two inverted current input sigrals-Xj an -Yj as a first output signal Wj based on the two previous input signals Xj-1 and Yj1 ; and
(f) choosing one of the current exclusive-ORed signal Goy and the inverted current exclusive-ORed signal- (Xj#Yj) as a second output signal Z. based on the two previous input signa's X. and Yj-1.
According to the present invention there is also provided
a post-coding apparatus for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder is equipped with the post-coding apparatus itself and two binary convolutional decoders and the apparatus converts a pair of current input signals X and Yj to a pair of output signals W. and Zj in which phase errors are corrected, the apparatus comprising :
two delaying means for delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals Xj-1 and Y. ;
two inverters for inverting the two current input signals
Xj and Yj, respectively, to generate two inverted current input signals-X, and-Y, ;
en exclusive-OR gate for exclusive-ORing the two current input signals Xj and Yj to generate a previous exclusive-ORed signal Xj#Yj; an inverter for inverting the current exclusive-ORed signal Xj#Yj to generate an inverted current exclusive-ORed signal - (Xj#Yj); a selector for selecting one of the two current input signals X. and Yj and the two inverted current input signals -X and-Yj as a first output signal W. based on the twc previous input signals Xj1 and Yj1 ; and
a chooser for choosing one of the current exclusive-ORed signal Xj#Yj and the inverted current exclusive-ORed signal # (Xj#Yj) as a second output signal Z. based on the two previous input signals Xj-1 and Yj-1.
~.
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which :
Fig. 1 shows a block diagram of a conventional cable transmission network ;
Figs. 2A and 2B present block diagrams of a conventional 64-ary quadrature amplitude modulation (QAM) trellis coded modulation (TCM) encoder and decoder, respectively ;
Fig. 3 describes a block diagram of a conventional differential post-coder ;
Fig. 4 illustrates a block diagram of a differential post-coder in accordance with the present invention ; and
Fig. 5 provides a block diagram of another differential post-coder in accordance with the present invention.
Referring to Table 1, there is illustrated two output signals W. and Z. corresponding to two current input signals Xi and Y ans two previous input signals Xj1 and Y. based on
Eq. 2 in the differential post-coder 37-3 shown in Fig. 2B.
If two current input signals are equal to two previous input signals, respectively, so that there is no quadrant phase change, two output signals M. and Zj are'0'and'0', respectively. If a quadrant phase change between the current input signals and the previous input signals is 90 degree, Wj ='0'and Zj = 1'; if a quadrant phase change therebetween is 180 degree, W. ='1'and Z-='CT ; and, if a quadrant phase change therebetween is 270 degree, M. = '1' and Zj = '1'.
[Table 1]
current input previous input output Xj Yj Xj-1 Yj-1 Wj Zj 0 0 0 0 0 0 0 0 0 1 1 1 001001 0 0 1 1 1 0 010001 0 1 0 1 0 0 0 1 1 0 1 0 011111 1 0 0 0 1 1 100110 101000 1 0 1 1 0 1 1 1 0 0 1 0 110101 1 1 1 0 1 1 1 1 1 1 0 0 Referring to Table 2, there are shown input and output characteristics between the two current input signals
Xj and Yj and the two output signals W. and Z. in accordance with one aspect of the present invention. Two current input signals Xj = '0' and Yj ='0'correspond to two output signals W = Y and Zj = X@Y ; two current input signals Xj. ='0' and Y. ='1'correspond to two output signals Wj = Xj-1 and Zj = # (Xj-1#Yj-1) ; two current input signals X. ='1'and Y-='0' correspond to two output signals Wj = -Xj-1 and Zj = -(Xj-1#Yj-1) ; and two current input signals X = '1' and Yj = '1' correspond to two output signals Wj = -Yj-1 and Zj = Xj-1#Yj-1, wherein '-' represents a logically'NOT'operation. That is to say, in accordance with the combination of the two current input signals X and Yj, one of X,-J, Yj-1, #Xj-1 and #Yj-1 is selected as the first output signal Wj ; and either Xj-1#Yj-1 or -(Xj-1#Yj-1) is selected as the second output signal Zj.
[Table 2]
current input output Xj Yj Wj Zj 0 0 Yj-1 Xj-1#Yj-1 0 1 Xj-1 # (Xj-1#Yj-1) 1 0 #Xj-1 #(Xj-1#Yj-1) 1 1 #Yj-1 Xj-1#Yj-1 Referring to Fig. 4, there is illustrated a differential post-coder of a TCM decoder in a digital cable transmission system in accordance with a preferred embodiment of the present invention, wherein the TCM decoder is equipped with two binary convolutional decoders and the differential postcoder, wherein the differential post-coder converts a pair of input signals Xj and Yj to a pair of output signals W and Z in which phase errors are corrected.
Each pair of input signals Xj and Yj may be treated as a pair of current input signals. A first current input signal Xi from each pair of input signals is provided to a first delay 41, a current exclusive-OR (XOR) gate 46 and a first selector 48 ; and a second, i. e., the other, current input signal Yj from each pair of input signals is provided to a second delay 42, the current exclusive-OR gate 46 and the first selector 48.
At the first delay 41, the first current input signal X is delayed by one bit so that a delayed input signal is provided as a first previous input signal X. to a first inverter 43, a previous exclusive-OR gate 47 and the first selector 48. At the second delay 42, the second current input signal Yj is delayed by one bit so that a delayed input signal is provided as a second previous input signal Y,-l to a second inverter 44, the previous exclusive-OR gate 47 and the first selector 48.
At the first and the second inverters 43 and 44, the first and the second previous input signals Xj and Yj1 are inverted as a first and a second inverted previous input signals #Xj-1 and-Yjl, respectively, both of which are then provided to the first selector 48.
At the first selector 48, e. g., a 4 : 1 multiplexor, both the first and the second current input signals X and Yj are used as first control signals so that one of the first and the second previous input signals X and Yj the second inverted previous input signals #Xj-1 and-Yj1 is selected as a first output Wj based on the first and the second current input signals X and Yj in accordance with
Table 2.
In the meantime, at the current exclusive-OR gate 46, two current input signals Xj and Yj are exclusive-ORed so that a current exclusive-ORed signal X is provided to a second selector 49 as a second control signal.
At the previous exclusive-OR gate 47, two previous input signals Xj-1 and Y., are exclusive-ORed so that a previous exclusive-ORed signal X.. @Y.. is provided to the second selector 49 and a third inverter 45 ; and, at the third inverter 45, the previous exclusive-ORed signal Xj-1#Yj-1 is inverted so that an inverted previous exclusive-ORed signal #(Xj-1#Yj-1) is provided to the second selector 49.
At the second selector 49, e. g., a 2 : 1 multiplexor, the current exclusive-ORed signal XjY. is used as a second control signal so that either the previous exclusive-ORed signal Xj-1#Yj-1 or the inverted previous exclusive-ORec signal - may be selected as a second output signal Zj based on the first and the second current input signals Xj and Yj in accordance with Table 2.
[Table 3]
previous input output Xj-1 Yj-1 wj Zj 0 0 Xj Xj#Yj 0 1 #Yj #(Xj#Yj) 1 0 Yj #(Xj#Yj) 1 1 #Xj Xj#Yj Referring to Table 3, there are shown input and output characteristics between the two previous input signals Xjl and
Yj-1 and the two output signals Wj and Z in accordance with another aspect of the present invention. Two previous input signals Xj-1 = '0' and Yj-1 = '0' correspond to two output signals W = Xj and Z = XYj ; two previous input signals X ='C'and Y-. ='1'correspond to two output signals Wj = #Yj and Z. =- (X. @Y.) ; two previous input signals Xj-1 = '1' and Yj-1 ='0'correspond to two output signals Wj = Yj and Z. = - (Xj#Yj) ; and two previous input signals Xj-1 = '1' and Yj-1 = '1'correspond to two output signals Wj = #Xj and Zj = Xj#Yj, wherein'-'represents a logically'NOT'operation. That is to say, in accordance with a combination of the two previous input signals X, and Yj-1, one of Xj, Yj, and #Yj is selected as the first output signal Wj ; and either Xj#Yj or - (Xj@Yj) is selected as the second output signal Zj.
Referring to Fig. 5, there is illustrated a differential post-coder of a TCM decoder in a digital cable television system in accordance with another preferred embodiment of the present invention, wherein the differential post-coder converts a pair of current input signals X and Yj to a pair of output signals Wj and Z in which phase errors are corrected.
A first current input signal Xj from each pair of input signals is provided to a first delay 51, a first inverter 53, a current exclusive-OR gate 56 and a first selector 58 ; and a second, i. e., the other, current input signal Yj from each pair of input signals is provided to a second delay 52, a second inverter 54, the current exclusive-OR gate 56 and the first selector 58.
At the first delay 51, the first current input signal X is delayed by one bit so that the delayed input signal is provided =. s a first previous input signal X. to a previous exclusive-OR gate 57 and the first selector 58. At the second delay 52, the second current input signal Yj is delayed by one bit so that the delayed input signal is provided as a second previous input signal Yjl to the previous exclusive-OR gate 57 and the first selector 58.
At the first and the second inverters 53 and 54, the first and the second current input signals X and Yj are inverted as a first and a second inverted current input signals #Xj and #Yj, respectively, both of which are then provided to the first selector 58.
At the first selector 58, e. g., a 4 : 1 multiplexor, both the first and the second previous input signals X. and Yj-1 are used as first control signals so that one of the first and the second current input signals X and Yj and the first and the second inverted current input signales-j and-Yj is selected as a first output W based on the first and the second previous input signals Xj-1 and Y., in accordance with
Table 3.
In the meantime, at the previous exclusive-OR gate 57, two previous input signals Xjl and Yjl are exclusive-ORed so that a previous exclusive-ORed signal Xj-1#Yj-1 is provided to a second selector 59 as a second control signal.
At the current exclusive-OR gate 56, two current input signals Xj and Yj are exclusive-ORed so that a current exclusive-ORed signal X, is provided to the second selector 59 and a third inverter 55 ; and, at the third inverter 55, the current exclusive-ORed signal Xj@Yj is inverted that that inverted current exclusive-ORed signal- (Xj@Y.) is provided to the second selector 59.
At the second selector 59, e. g., a 2 : 1 multiplexor, the previous exclusive-ORed signal Xj-1#Yj-1 is used as the second control signal so that either the current exclusive-ORed signal Xj#Yj or the inverted current exclusive-ORed signal # (Xj#Yj) may be selected as a second output signal Zj based on the first and the second previous input signals Xj and Yj in accordance with Table 3.
Since only one inverter and one selector should be operated successively in order to calculate the first output signal W. and one exclusive-OR gate, one inverter and one selector should be operated successively in order to calculate the second output signal Zj, the differential post-coding can be realized with two or at most three steps.
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Claims (14)
- Claimes 1. A post-coding method for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder includes a differential post-coder and two binary convolutional decoders and the differential post-coder converts a pair of current input signals X and Yl to a pair of output signals Wj and Z in which phase errors are corrected, the method comprising the steps of : (a) delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals Xjt and Yj-1 ; (b) inverting the two previous input signals Xi and Yj-1, respectively, to generate two inverted previous input signals #Xj-1 and ; (c) exclusive-ORing the two previous input signals X and Y.. to generate a previous exclusive-ORed signal Xj-1#Yj-1; (d) inverting the previous exclusive-ORed signal Xj-1#Yj-1 to generate an inverted previous exclusive-ORed signal # (Xj-1#Yj-1); (e) selecting one of the two previous input signals X., and Yj-1 and the two inverted previous input signals-Xj1 and -Y., as a first output signal Wj based on the two current input signals X. and Yj ; and (f) choosing one of the previous exclusive-ORed signal Xj-1#Yj-1 and the inverted previous exclusive-ORed signal # (Xj-1#Yj-1) as a second output signal Zj based on the two current input signals Xj and Yj
- 2. The method as recited in claim 1, wherein said choosing step (f) includes the steps of : (fl) exclusive-ORing the two current input signals Xi an Yj to generate a current exclusive-ORed signal X, ; and (f2) determining one of the previous exclusive-ORed signal Xj-1#Yj-1 and the inverted previous exclusive-ORed signal - as the second output signal Z. based on the current exclusive-ORed signal Xj#Yj.
- 3. The method as recited in claim 2, wherein, if a pair of current input signals X and Yj is equal to'00','01','10' and '11'. the first output signal Wj corresponds to Yj-1, Xj-1, #xj-1 and-Yj1, respectively, and, if the current exclusive ORed signal X is equal to'0'and'1', the second output signal Z corresponds to Xj-1#Yj-1 and # (Xj-1#Yj-1), respectviely.
- 4. A post-coding apparatus for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder is equipped with the post-coding apparatus itself and d two binary convolutional decoders and the apparatus converts a pair of current input signals X and Yj to a pair of output signals Wj and ZJ ln which phase errors are corrected, the apparatus comprising : two delaying means for delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals X. and Yj-1; two inverters for inverting the two previous input signals X. and Yj-1, respectively, to generate two inverted previous input signals #Xj-1 and #Yj-1 ; an exclusive-OR gates for exclusive-ORing the two previous input signals Xj and Yj1 to generate a previous exclusive-ORed signal Xj-1#Yj-1; an inverter for inverting the previous exclusive-ORed signal j-1#Yj-1 to generate an inverted previous exclusive-ORed signal- ; a selector for selecting one of the two previous input signals Xj-1 and Yj-1 and the two inverted previous input signals #Xj-1 and #Yj-1 as a first output signal Wj based on the two current input signals X and Yj ; and a chooser for choosing one of the previous exclusive-ORed signal X-, SY., and the inverted previous exclusive-ORed signal - as a second output signal Z. based on the two current input signals Xj and Yj.
- 5. The apparatus as recited in claim 4, wherein said chooser includes : an exclusive-OR gate for exclusive-ORing the two current input signals Xj and Yj to generate a current exclusive-ORed signal X. Yj ; and means for determining one of the previous exclusive-ORed signal X Y and the inverted previous exclusive-ORed signal # (Xj-1#Yj-1) as the second output signal Z based on the current exclusive-ORed signal Xj#Yj,
- 6. The apparatus as recited in claim 5, wherein, if a pair of current input signals X and Yj is equal to'00','01', '10'and'11', the first output signal Wj corresponds to Yj-j, Xj-1, #Xj-1 and #Yj-1, respectively, and, if the current exclusive-ORed signal X is equal to'0'and'1', the second output signal Z corresponds to Xj-1#Yj-1 and # (Xj-1#Yj-1), respectively.
- 7. A post-coding method for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder includes a differential post-coder and two binary convolutional decoders and the differential post-coder converts a pair of current inpur signals Xj and Yj to a pair of output signals Wj and Zj in which phase errors are corrected, the method comprising the steps of : (a) delaying two current input signals Xj and Yj by one bit, respectively, to generate two previous input signals X and Yj1 ; (b) inverting the two current input signals Xj and Yj, respectively, to generate two inverted current input signals #Xj and #Yj; (c) exclusive-ORing the two current input signals Xj and Yj to generate a previous exclusive-ORed signal X, ; (d) inverting the current exclusive-ORed signal X to generate an inverted previous exclusive-ORed signal #(Xj#Yj) ; (e) selecting one of the two current input signals Xj and Yj and the two inverted current input signales-j and-Yj as a first output signal Wj based on the two previous input signals X. and Yj-1 ; and (f) choosing one of the current exclusive-ORed signal XiE) and the inverted current exclusive-ORed signal- (Xj#Yj) as a second output signal Z based on the two previous input signals Xj-1 and Yj-1.
- 8. The method as recited in claim 7, wherein said choosing step (f) includes the steps of : (fl) exclusive-ORing the two previous input signals X and Y., to generate a previous exclusive-ORed signal Xj-1#Yj-1; end (f2) determining one of the current exclusive-ORed signal Xj#Yj and the inverted current exclusive-ORed signal #(Xj#Yj) as the second output signal Z based on the previous exclusive-ORed signal Xj-1#Yj-1
- 9. The method as recited in claim 8, wherein, if a pair of previous input signals X., and Yj1 is equal to'00','01', '10'and'11', the first output signal Wj corresponds to Xj, #Yj Yj and-Xj, respectively, and, if the previous exclusive ORed signal Xj-1#Yj-1 si equal to'0'and'1', the second output signal Zj corresponds to XI and #(Xj#Yj), respectively.
- 10. A post-coding apparatus for use in a trellis-coded modulation (TCM) decoder, wherein the TCM decoder is equipped with the post-coding apparatus itself and two binary convolutional decoders and the apparatus converts a pair of current input signals Xi and Yj to a pair of output signals W. and Xj in which phase errors are corrected, the apparatus comprising : two delaying means for delaying two current input signals Xi and Y boy one bit, respectively, to generate two previous input signals Xj1 and Yj1 ; two inverters for inverting the two current input signals Xj and Yj, respectively, to generate two inverted current input signales-j and-Yj ; an exclusive-OR gate for exclusive-ORing the two current input signals Xj and Yj to generate a previous exclusive-ORed signal XiE) ; an inverter for inverting the current exclusive-ORed signal Xj@Yj to generate an inverted current exclusive-ORed signal #(Xj#Yj) ; a selector for selecting one of the two current input signals Xj and Yj and the two inverted current input signals -Xi and-Yj as a first output signal Wj based on the two previous input signals Xj, and Yj-1 ; and a chooser for choosing one of the current exclusive-ORed signal Xi and the inverted current exclusive-ORed signal #(Xj#Yj) as a second output signal Zj based on the two previous input signals Xj-1 and Yj-1.
- 11. The apparatus as recited in claim 10, wherein said chooser includes : an exclusive-OR gate for exclusive-ORing the two previous input signals Xj, and Y., to generate a previous exclusive ORed signal Xj-1#Yj-1; and means for determining one of the current exclusive-ORed signal Xi and the inverted current exclusive-ORed signal - as the second output signal Z. based on the previous exclusive-ORed signal Xj-1#Yj-1.
- 12. The apparatus as recited in claim 11, wherein, if a pair of previous input signals X:.. and Y.. is equal to'00','01', '10'and'11', the first output signal W. corresponds to Xj, -Yj, Yj and-Xj, respectively, and, if the previous exclusive ORed signal Xj-1#Yj-1 is equal to'0'and'1', the second output signal j corresponds to X. @Y. and- (X. @Y.), respectively.
- 13. An apparatus constructed and arrange substantially as herein described with reference to or as shown in Figures 4 and 5 of the accompanying drawings.
- 14. A method substantially as herein described with reference to or as shown in Figures 4 to 5 of the accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970073163A KR19990053518A (en) | 1997-12-24 | 1997-12-24 | Differential postcoder of cable modem downstream system TCM decoder |
| KR1019970073162A KR19990053517A (en) | 1997-12-24 | 1997-12-24 | Differential postcoder of cable modem downstream system TCM decoder |
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| Publication Number | Publication Date |
|---|---|
| GB9819478D0 GB9819478D0 (en) | 1998-10-28 |
| GB2332835A true GB2332835A (en) | 1999-06-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9819478A Withdrawn GB2332835A (en) | 1997-12-24 | 1998-09-07 | Differential post-coder for a tcm decoder |
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| GB (1) | GB2332835A (en) |
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| EP1363404A1 (en) * | 2002-05-08 | 2003-11-19 | Micronas GmbH | Pulse-width modulated sensor output signal |
| DE102004003103A1 (en) * | 2004-01-19 | 2005-08-18 | Christian-Albrechts-Universität Zu Kiel | Circuit arrangement for precoding digital signals for message transmission by means of optical DQPSK modulation |
| US7310768B2 (en) * | 2000-01-28 | 2007-12-18 | Conexant Systems, Inc. | Iterative decoder employing multiple external code error checks to lower the error floor |
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| US5307377A (en) * | 1990-10-09 | 1994-04-26 | U.S. Philips Corporation | System for modulating/demodulating digital signals transmitted with encoded modulation |
| EP0716529A2 (en) * | 1994-12-09 | 1996-06-12 | General Instrument Corporation Of Delaware | Rotationally invariant trellis code |
| US5757856A (en) * | 1993-11-30 | 1998-05-26 | Alcatel N.V. | Differential coder and decoder for pragmatic approach trellis-coded 8-PSK modulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5307377A (en) * | 1990-10-09 | 1994-04-26 | U.S. Philips Corporation | System for modulating/demodulating digital signals transmitted with encoded modulation |
| US5757856A (en) * | 1993-11-30 | 1998-05-26 | Alcatel N.V. | Differential coder and decoder for pragmatic approach trellis-coded 8-PSK modulation |
| EP0716529A2 (en) * | 1994-12-09 | 1996-06-12 | General Instrument Corporation Of Delaware | Rotationally invariant trellis code |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7310768B2 (en) * | 2000-01-28 | 2007-12-18 | Conexant Systems, Inc. | Iterative decoder employing multiple external code error checks to lower the error floor |
| US7568147B2 (en) | 2000-01-28 | 2009-07-28 | Nxp B.V. | Iterative decoder employing multiple external code error checks to lower the error floor |
| EP1363404A1 (en) * | 2002-05-08 | 2003-11-19 | Micronas GmbH | Pulse-width modulated sensor output signal |
| DE10220844B4 (en) * | 2002-05-08 | 2006-05-11 | Micronas Gmbh | Method for transmitting measured values by means of a pulse-modulated signal and associated sensor and system with sensor |
| DE102004003103A1 (en) * | 2004-01-19 | 2005-08-18 | Christian-Albrechts-Universität Zu Kiel | Circuit arrangement for precoding digital signals for message transmission by means of optical DQPSK modulation |
| DE102004003103B4 (en) * | 2004-01-19 | 2011-06-01 | Christian-Albrechts-Universität Zu Kiel | Circuit arrangement for precoding digital signals for message transmission by means of optical DQPSK modulation |
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|---|---|
| GB9819478D0 (en) | 1998-10-28 |
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