JPH10107865A - Hierarchical transmission system and transmitter-receiver therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hierarchical transmission system in which an interleave circuit is used in common and the distance of interleave is made longer as to a hierarchy small in multi-valued level. SOLUTION: When input data are 16QAM, data of 4-bit per one symbol are fed to a selection circuit 15 via a path B, where required data are selected, the selected data are de-interleaved for each symbol by a de-interleave circuit 52 and required processed-data are selected by a selection circuit 53 and fed to a forward error correction(FEC) decoder 54. When input data are quadrature phase shift keying(QPSK) data, data of 2-bit per symbol passes through a path A, latched partly in a latch circuit 56 via a switch 55 and outputted in pairs with an output at a side of a through-path 57. Each output of the through-path 57 and the latch circuit 56 is a 2-bit output and both data are 4-bit data (2-symbol) in total and fed to the selection circuit 51 and the data are processed afterward similarly to the case with the 16QAM data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a hierarchical transmission system for hierarchically transmitting a digitally modulated signal and transmitting and receiving apparatus.

[0002]

2. Description of the Related Art Hierarchical transmission systems have recently been widely used in wireless mobile reception systems and the like. This hierarchical transmission is to transmit digital modulation signals of various multi-levels. For example, when the transmission path condition is good, a modulation signal of a large multi-level (64 QAM, etc.) is transmitted and transmitted. A transmission scheme has been attempted in which the efficiency is increased and a modulated signal (QPSK or the like) having a small multilevel level is transmitted to reduce the influence of noise when the transmission path condition is poor.

At present, interleaving of hierarchical transmission signals is
This is performed for each symbol using a common interleave circuit in each layer. However, such a conventional system has a problem that the interleave distance is constant regardless of the hierarchy. In addition, there is a problem in that the number of bits per symbol is small in a hierarchy having a small multilevel level, so that the memory used is wasted.

FIG. 5 is a diagram showing the overall configuration of a decoding device on the receiving side in the hierarchical transmission system.
And FEC (Forward Error Correction)
And a circuit 12. Here, for example, a convolutional interleave having a depth of 3 and a cell length of 1 is used as interleaving, and QPSK and 16QA which are hard-decided are used.
Consider a decoding device that can receive M.

FIG. 6 shows a configuration of a conventional interleave circuit 11. 6, reference numeral 111 denotes a switch for switching a data output path for each symbol, and 112 denotes a switch 1
This switch selects and outputs the data of the corresponding path in synchronization with the switching of No. 11. The first path is through, the second path includes a delay circuit 113 that performs delay processing for one symbol, and the third path includes two delay circuits 114 and 115 that perform delay processing for one symbol each in series. .

As described above, in the conventional interleaving circuit 11 for interleaving every symbol, each symbol is interleaved before and after interleaving. The symbol "0" and "1" adjacent to each other before interleaving are separated by four by interleaving (interleave distance 4).

As can be seen from the above relationship, in the conventional interleaving method, since interleaving is performed for each symbol, the above-mentioned distance relationship does not change depending on the hierarchy, and the interleave distance becomes 4 in both QPSK and 16QAM. I will.

[0008] In interleaving for each symbol, a layer (64Q
AM: 4 bits), a holding unit or a memory is prepared. However, in a hierarchy having a small number of bits and a small multilevel level (QPSK: 2 bits), the prepared holding unit or the memory is maximized. Never use
Poor efficiency (only 2 bits out of 4 bits).

Further, in recent hierarchical transmission, when the state of the traveling path is poor, a layer having a small multilevel level is transmitted at the same time as interleaving of a layer having a small multilevel level further separates adjacent signals (interleave). There is a demand that it is desirable to make it less susceptible to burst noise and the like (by increasing the distance). However, in order to realize such a demand, it is necessary to provide an individual interleave device for each multilevel level.

Here, in response to the demand for increasing the interleave distance depending on the hierarchy as described above, it has conventionally been considered that the interleave processing is required for each hierarchy as shown in FIG.

In FIG. 7, deinterleaving circuits 21, 22,..., 2n each input a received signal and perform deinterleaving for each layer. The outputs of the de-interleave circuits 21, 22,..., 2n are selected for each hierarchical mode by the multiplexer circuit 24,
Error correction is performed in step 5 to obtain decoded data.

As an example, hard-determined QPSK and 16Q
Consider a decoding device capable of receiving AM. It is desired that the interleave distance of QPSK be larger than that of 16QAM. Therefore, for example, FIG. 8A shows a configuration of an interleaving circuit of QPSK when performing convolutional interleaving with a depth of 6 and a cell length of 1, and performs a convolutional interleaving with a depth of 3 and a cell length of 1. FIG. 8B shows the configuration of the 16QAM interleave circuit.

In FIG. 8A, switches 31 and 32 switch data transmission paths, and reference numerals 33 to 38 denote delay circuits for delaying input data by one symbol. FIG.
In (b), 41 and 42 are switches for switching a data transmission path, and 43 to 45 are delay circuits for delaying input data by one symbol.

In this case, the interleaving of QPSK shown in FIG. Although the interleave distance is less than twice that of 16QAM, a de-interleave circuit is required for each layer as shown in FIG.

When this interleaving is realized by a RAM, QPSK and 16QAM use different RAMs, and address control is also performed separately. 16QAM has 4 bits per symbol, while QPSK has 2 bits per symbol. Therefore, when a specific transmission rate is set, the address control speed of QPSK needs to be doubled compared to the address control speed of 16QAM. This required more power.

[0016]

As described above, in the conventional hierarchical transmission system, when performing the interleaving of the hierarchical transmission signal, the same circuit is used for each layer for each symbol, and each layer is interleaved. How can only obtain a certain interleave distance regardless.

Further, in a hierarchy having a small multilevel level, 1
Since the number of bits per symbol is small, the holding means or the memory is wasted. Further, in order to increase the interleave distance in a hierarchy having a small multilevel level, a separate interleave circuit must be used for each hierarchy, and a large memory is required.

Further, when the interleave is constituted by a RAM, the address control speed needs to be several times faster in a hierarchy having a small multilevel level than in a hierarchy having a large multilevel level.

An object of the present invention is to solve the above-mentioned problems and to provide a hierarchical transmission system and a transmission / reception apparatus which can use a common interleave circuit and can increase the interleave distance for a hierarchy having a small multilevel level. With the goal.

[0020]

In order to achieve the above object, the present invention has the following arrangement. That is, the first invention is a hierarchical transmission system having a plurality of layers having different multilevel levels, wherein the interleaving distance of a layer having a smaller multilevel level among the plurality of layers is determined. In this configuration, the interleaving process is performed in common for each layer.

In the second invention, the transmission symbols are K bits / symbol (A0 hierarchy), K × J1 bits / symbol (A1 hierarchy), and K × J1 × J2 bits / symbol (A
K × ΠJI (initial value i is 1 to N-1) In a layer transmission system having N layers of bits / symbol (AN-1 layer) (JN-1: integer), any layer Ag-1 Is the interleave distance of the layer Ag-1-1) = (the interleave distance of the layer Ag-1) × Jg
(Jg: integer).

In the third invention, K bits per symbol (A0 hierarchy) and K × J1 bits (A
K × J1 × J2 bits (A2 layer) ... K × Π
Ji (initial value i is 1 to N-1) bits (AN-1 hierarchy)
In a hierarchical transmission system having N layers where quantization of (JN-1: integer) is required, the interleave distance of an arbitrary layer Ag-1 is (interleave distance of layer Ag-1-1) =
It is assumed that (interleave distance of hierarchy Ag−1) × Jg (Jg: integer).

According to a fourth aspect of the present invention, in the decoding apparatus using the hierarchical transmission method according to the second and third aspects, a set forming means for forming a set of Jg symbols as a deinterleave input of the arbitrary layer Ag-1. And deinterleaving means for deinterleaving the set of Jg symbols as one unit, and output means for outputting the unit deinterleaved by this means as one symbol.

According to a fifth aspect of the present invention, in the decoding device according to the fourth aspect of the present invention, the deinterleave means is constituted by a memory circuit. According to a sixth aspect of the present invention, in the coding apparatus using the hierarchical transmission method according to the second or third aspect, Jg is used as an input of the interleave of the arbitrary layer Ag-1.
Set forming means for forming a set of symbols;
Interleaving means for interleaving symbols as one unit, and one unit interleaved by this means
Output means for outputting as a symbol.

According to a seventh aspect of the present invention, in the encoding device according to the sixth aspect, the interleaving means is constituted by a memory circuit. An eighth aspect of the present invention is an interleaving apparatus characterized in that a group of several symbols is interleaved in accordance with the interleaving distance.

According to the above configuration, it is possible to use a common interleave circuit corresponding to various hierarchies, and to increase the interleave distance of hierarchies having a small multilevel level, so that it is resistant to noise on the transmission path. It will be. Further, the memory can be reduced and the power consumption can be reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is an overall configuration diagram of a decoding device that can receive a hard-decided two-layer modulated signal of QPSK and 16QAM. Here, for simplicity of explanation, the interleave is depth 3 and cell length 1
Convolutional interleave.

In FIG. 1, demodulated received signals (input data) I and Q data are branched into two and input to paths A and B. When the input data is 16 QAM, 4-bit data per symbol passes through path B
Supplied to Here, the selection circuit 51 outputs the hierarchical mode signal M
Select data according to OD. The output data of the selection circuit 51 is supplied to a de-interleave circuit 52, which performs a de-interleave process for each symbol, and
Supplied to The output data of the selection circuit 53 is FE
It is supplied to the C decoder 54.

An example of the above 16QAM operation will be described below. First, input data is supplied from the path B to the de-interleave circuit 52 through the selection circuit 51.

The data sequence before interleaving is 0, 1,
2,3,4,5,6,7,8,9,10,11,12,
The order is… On the other hand, the data sequence after de-interleaving is 0, *, *, 3, 1, *, 6, 4,
The order is 2, 9, 7, 5, 12,... (Each of the numerical data is 4 bits (one symbol)).

The 4-bit data output from the de-interleave circuit 52 is supplied to a selection circuit 53, and the output data is supplied to an FEC decoder 54. When the input data is QPSK data, 2-bit data of one symbol passes through the path A, and is sequentially supplied to the holding circuits 56 having the same number of holding capacity as the interleave depth by the path switching switch 55.

When data is stored in all the holding circuits 56, the next data is led out to a through path 57 by a path switching switch 55. At the same time, data is also output from the holding circuit 56. Through path 57 and holding circuit 5
Each of the output data 6 is 2 bits, and both data are supplied to the selection circuit 51 as a total of 4 bits (2 symbols).

In this case, the 2-bit data from the holding circuit 56 is set as the upper bit, and the 2-bit data from the through path 57 is set as the lower bit. The 4-bit (2 symbols) output from the selection circuit 51 is supplied to a de-interleave circuit 52,
A de-interleave process is performed for a set of two symbols. This de-interleave circuit 52 has the same configuration as the configuration shown in FIG.
21, 522 and a delay circuit 5 for delaying in units of two symbols
23, 524, and 525.

4 from the de-interleave circuit 52
The bit output is divided into upper two bits and lower two bits, and supplied to the through path 58 and the holding circuit 59, respectively. At this time, the changeover switch 60 has selected the through path 58.

When data is stored in all areas of the holding circuit 59, the output of the holding circuit 59 is selected by the changeover switch 60 and supplied to the selection circuit 53. Holding circuit 59
When all of the data stored in the through-path is output, the data from the through path 58 is output by the changeover switch 60. Hereinafter, the same switching operation as described above is repeated.

An example of the above QPSK operation will be described below. (1) First, data 0, 1, 2, 3, 4, 5, to route A
, 6, 7, 8, 9, 10, 11, 12,... Are input (each of the numerical data is 2 bits).

(2) At this time, data 0, 1, and 2 are input to the holding circuit 56 using the switch 55. (3) Next, data is sent to the through path 57 using the switch 55. At the same time, the data is also output from the holding circuit 56 to make all the bits.

Here, it is assumed that the 2-bit data from the holding circuit 56 is the higher order and the data from the through path 57 is the lower order. That is, the output of the holding circuit 56 is in the order of 0, 1, 2 (upper 2 bits), and the output of the through path 57 is in the order of 3, 4, 5 (lower 2 bits).

(4) This data set (0 and 3, 1 and 4,
2 and 5) are sequentially input to the selection circuit 51. (5) Data 6, 7, and 8 are sequentially input to the holding circuit 56 again using the switch 55.

(6) Next, the switch 55 is switched to send data to the through path 57, and at the same time, to output data from the holding circuit 56. That is, the output of the holding circuit 56 is in the order of 6, 7 and 8, and the output of the through path 57 is 9
The order is 10,11.

(7) This data set (6 and 9, 7 and 1
0, 8 and 11) are input to the selection circuit 51. (8) The above processing procedures (2) to (4) are repeated.

(9) On the other hand, the output data from the selection means 51 is supplied to the de-interleave circuit 52. Before interleaving, 0 and 3, 1 and 4, 2 and 5, 6 and 9,
7 and 10, 8 and 11, 12 and 15, 13 and 16, 14 and 17 ...
And 3, * and *, * and *, 6 and 9, 1 and 4, * and *, 12
, 15, 7 and 10, 2 and 5...

(10) The 4-bit output data from the de-interleave circuit 52 is output every two bits (one symbol).
It is supplied to the through path 58 and the holding circuit 59. At this time, the switch 60 selects the through path 58 and outputs it. The through path 58 outputs 0, *, * in order, and the holding circuit 59 outputs 3, *, * in order.

(11) When the data is stored in all the areas of the holding circuit 59, the data is output from the holding circuit 59 by the switching operation of the switch 60. (12) Repeat (8) to (9), and from switch 60, data 0, *, *, 3, *, *, 6, 1, *, 9, 4,
*, 12, 7, 2, ... are sequentially output.

(13) The data output from the switch 60 is supplied to the selection circuit 53, and the output data from the selection circuit 53 is supplied to the FEC decoder 54. Here, for the sake of simplicity, convolutional interleaving with a depth of 3 and a cell length of 1 has been described as an example, but in practice, convolutional interleaving generally has a depth of about 10 and a cell length of about 20.

Taking this into consideration, when the interleave distance of a layer having a small multilevel level is increased, the interleaving circuit is switched between before and after the interleave circuit in the configuration according to the present invention, compared with having an interleave circuit for each layer separately. Since the switches, holding circuits, through paths, and the like are arranged and the interleave circuit is shared, the circuit scale can be sufficiently reduced.

FIG. 2 shows QPSK, 64QA which is soft-decision.
FIG. 11 is an overall configuration diagram of a decoding device that can receive a two-level modulated signal of M. Here again, for simplicity of explanation, the interleaving is assumed to be convolutional interleaving having a depth of 3 and a cell length of 1.

The demodulated received signals (input data) I and Q
Data is branched to paths A and B. Input data is 64Q
In the case of AM, data of 6 bits per symbol is quantized to, for example, 8 bits. This 8-bit data is
The signal is supplied to the selection circuit 61 through the path B.

Here, the selection circuit 61 outputs the hierarchical mode signal M
Select data by OD. The output data of the selection circuit 62 is supplied to a de-interleave circuit 63, where the output data is de-interleaved for each symbol, and
Supplied to The output of the selection circuit 63 is an FEC decoder 64
Supplied to

The de-interleave circuit 63
Switches 631 and 632 and delay circuits 623 and 624
625. Since the processing operation is the same as that of the above-described embodiment, the description is omitted here.

When the input data is QPSK data,
Data of 2 bits per symbol is quantized to, for example, 4 bits. The 4-bit data passes through the path A and is sequentially input to a holding circuit 66 having a holding capacity equal to the interleave depth according to the switching operation of the switch 65.

When the data is stored in all the areas of the holding circuit 66, the switch 65 is used to
Send data to At the same time, the holding circuit 66 outputs data. As a result, the data having a total of 8 bits (2 symbols) is supplied to the selection circuit 61. Here, the 4-bit data from the holding circuit 66 is set to the high order, and the 4-bit data from the through path 67 is set to the low order.

The 8-bit (two symbols) output from the selection circuit 61 is supplied to a de-interleave circuit 62,
A de-interleave process is performed on a set of symbols. The 8-bit output from the de-interleave circuit 62 is divided into upper 4 bits and lower 4 bits and supplied to the through path 68 and the holding circuit 69, respectively. At this time, the switch 70 has selected the through path 68.

When the data has been stored in all the holding circuits 69, the data from the holding circuit 69 is output using the switch 70. When all the data stored in the holding circuit 69 has been output, the data is output from the through path 68 using the switch 70. Hereinafter, the above switching operation is repeated.

Next, an embodiment in which an interleave is constituted by a RAM will be described with reference to FIG. Examples of hard-decided QPSK, 16QAM and 256QAM
Consider a decoding device that can receive the three layers described above. Here also, the interleaving is convolutional interleaving with a depth of 3 and a cell length of 1.

The demodulated received signals (input data) I and Q
Data is input to path A, path B, and path C. When the input data is 256 QAM, 8-bit data per symbol is supplied to the selection circuit 71 through the path C. Here, the selection circuit 71 selects and outputs data according to the hierarchical mode signal MOD.

The output of the selection circuit 71 is supplied to a RAM 72 constituting a de-interleave circuit, deinterleaved for each symbol, and supplied to a selection circuit 73. The output from the selection circuit 73 is supplied to the FEC decoder 74.

When the input data is 16 QAM, 4-bit data per symbol passes through the path B and is sequentially input via the switch 75 to the holding circuit 76 having the same number of holding capacity as the interleave depth.

When the data has been stored in all the holding circuits 76, the data is sent to the through path 77 using the switch 75. At the same time, data is output from the holding circuit 76. Here, the data of all 8 bits (2 symbols) is supplied to the selection circuit 71. Here, the 4-bit data output from the holding circuit 76 is set as the higher order,
The 4-bit data output from 7 is the lower order.

The 8-bit (2 symbols) output from the selection circuit 71 is supplied to a de-interleave RAM 72.
A de-interleave process is performed for a set of two symbols. The 8-bit output from the de-interleave RAM 72 is divided into upper 4 bits and lower 4 bits and supplied to the through path 78 and the holding circuit 79, respectively. At this time, the switch 80 is selecting the through path 78.

When the data has been stored in all the holding circuits 79, the data from the holding circuit 79 is output using the switch 80. When the input data is QPSK, 2-bit data per symbol passes through the path A, and is sequentially input to the holding circuits 83 having the same number of holding capacity as the interleave depth by the switching operation of the switch 81.

When data is stored in all of the holding circuits 83, the data is sequentially input to the holding circuits 84 having the same number of holding capacity as the interleave depth using the switch 81. When the data is stored in all the holding circuits 84, the data is sequentially input to the holding circuits 85 having the same number of holding capacity as the interleave depth using the switch 81.

When data is stored in all of the holding circuits 85, the data is sent to the through path 82 using the switch 81. At the same time, the data from the holding circuits 83, 84, 85 is also output. Here, the data of all 8 bits (4 symbols) is supplied to the selection circuit 71.

The 8-bit (four symbols) output from the selection circuit 71 is supplied to a de-interleave RAM 72, and a de-interleave process is performed on a set of four symbols. The 8-bit output from the de-interleave RAM 72 is supplied to the through path 86 and the holding circuits 87, 88,
89, two bits (one symbol) are input at a time. At this time, the switch 90 has selected the through path 86.

When the data is stored in all the areas of the holding circuits 87 to 89, the data is output from the holding circuit 87 by using the switch 90. When all the data stored in the holding circuit 87 is output, the data is output from the holding circuit 88 using the switch 90. After outputting all the data stored in the holding circuit 88, the switch 90 is used to output the data from the holding circuit 89.
When all the data stored in the holding circuit 89 is output, the data of the through path 86 is output using the switch 90. Hereinafter, the above switching operation is repeated.

In the above configuration, when the interleave processing is performed, the interleave distance can be increased in a hierarchy having a small multi-level level, and the RAM address control can be shared among the hierarchies. Further, the RAM access speed can be made to operate at the symbol rate of the hierarchy having a large multilevel level in any hierarchy regardless of the hierarchy.

Next, a description will be given of an embodiment of interleaving of a modulation scheme having a small multilevel level without performing hierarchical transmission with reference to FIG. Here, as an example, a decoding device that can receive hard-decided QPSK is considered.

The demodulated received signals (input data) I and Q
Data is input to paths A and B. The 2-bit data of one symbol passes through the path A and is sequentially input via the switch 91 to the holding circuit 92 having the same number of holding capacity as the interleave depth.

When data is stored in all of the holding circuits 92, the data is sent to the through path 93 using the switch 91. At the same time, the data is output from the holding circuit 92. Here, the data of all 4 bits (2 symbols) is supplied to a de-interleave circuit 94, and a de-interleave process is performed by combining two symbols.

The output from the de-interleave circuit 94 is supplied to the through path 95 and the holding circuit 96 every two bits (one symbol). At this time, the switch 97 is selecting the through path 95.

When the data has been stored in all the holding circuits 96, the switch 97 is used to output the data from the holding circuit 96. When all the data stored in the holding circuit 96 is output, the switch 97 selects the through path 95 and outputs the data to the FEC decoder 98. Hereinafter, the above switching operation is repeated.

The present invention is not limited to the above embodiments. For example, in the above embodiments, the holding circuit,
A case has been described in which the changeover switch, the selection circuit, and the de-interleave circuit are separately provided, and the operation of each of these circuits is performed.
(Digital Signal Processor) or the CPU may realize the operation of each of the above circuits by software.

In the above embodiment, QPSK, 16 QAM, 256 QAM, etc. have been described as examples of the modulation scheme. However, the present invention is not limited to this, and DQPSK, 1
The present invention can be applied to all kinds of bits having different numbers of bits representing one symbol, such as 6DQPSK, 16DAPSK, and 64DAPSK.

Further, as the interleaving, the above embodiment has been described taking convolutional interleaving as an example, but other interleaving schemes can be applied.

[0075]

As described above, according to the present invention, there is provided a hierarchical transmission system in which an interleave circuit is common and an interleave distance can be increased for a hierarchy having a small multilevel level, and a transmission / reception apparatus therefor. can do. In particular, by using a common interleave circuit corresponding to various layers, it is possible to increase the interleave distance of the layer with a small multilevel level, so that the layer with a small multilevel level is resistant to noise on the transmission path. Become. Further, the memory can be reduced and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of a hierarchical transmission system according to the present invention, in which a hard-decided two-layer transmission signal QPSK and 1
It is a block circuit diagram which shows the structure of the decoding device which can receive 6QAM.

FIG. 2 shows one embodiment of a hierarchical transmission system according to the present invention, which is QPSK and 1 that are two-layer transmission signals that are soft-decided.
It is a block circuit diagram which shows the structure of the decoding device which can receive 6QAM.

FIG. 3 shows one embodiment of a hierarchical transmission scheme according to the present invention, in which QPSK and three 1
FIG. 3 is an overall diagram of a decoding device using a RAM for interleaving capable of receiving 6QAM and 256QAM.

FIG. 4 is a block circuit diagram showing an interleaved configuration as one embodiment in a case where hierarchical transmission according to the present invention is not performed.

FIG. 5 is a block circuit diagram showing an entire configuration of a conventional decoding device capable of receiving a hierarchical transmission signal.

FIG. 6 is a block circuit diagram showing a configuration of a conventional de-interleave circuit.

FIG. 7 is a block circuit diagram showing an entire configuration of a conventional decoding device that changes an interleave distance for each layer.

FIG. 8A shows a conventional QPSK interleave circuit for changing the interleave distance for each layer, and FIG. 8B shows a conventional 16QAM interleave circuit for changing the interleave distance for each layer. It is a block circuit diagram showing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... De-interleave circuit 111, 112 ... Switch 113, 114, 115 ... Delay circuit 12 ... FEC circuit 21-2n ... De-interleave circuit 24 ... Multiplexer circuit 25 ... FEC circuit 31, 32 ... Switch 33-38 ... Delay circuit 41, 42 switches 43 to 45 delay circuits 51, 61, 71 selection circuits 52, 62, 72 deinterleave circuits (RAM) 53, 63, 73 selection circuits 54, 64, 74 FEC decoder 55 , 65, 75 ... switches 56, 66, 76 ... holding circuits 57, 67, 77 ... through paths 58, 68, 78 ... through paths 59, 69, 79 ... holding circuits 60, 70, 80 ... changeover switches 81 ... switches 82 ... through paths 83, 84, 85 ... holding circuit 86 ... through path 87, 88, 89 ... holding circuit 0 ... Switch 91 ... Switch 92 ... holding circuit 93 ... through ball 94 ... de-interleave circuit 95 ... through ball 96 ... holding circuit 97 ... Switch 98 ... FEC decoder

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Keisuke Harada, Inventor Next-generation Digital Television Broadcasting System Laboratory, 5-2-2-8 Akasaka, Minato-ku, Tokyo (72) Inventor Rumi Tanabe Shinsugita, Isogo-ku, Yokohama-shi, Kanagawa 8 Tochiba Multimedia Technology Research Laboratories

Claims (8)

[Claims] In a hierarchical transmission system having a plurality of layers having different levels of multi-levels, an interleave distance of a layer having a smaller level of multi-levels is compared with a layer having a higher level of levels of multi-levels. Broadly speaking, a hierarchical transmission method characterized in that interleave processing is performed in common for each layer. 2. The transmission symbol is K bits / symbol (A0
Hierarchy), K × J1 bits / symbol (A1 hierarchy), K ×
J1 × J2 bits / symbol (A2 layer) ... K × ΠJi
In the hierarchical transmission scheme having N layers of (initial value i is 1 to N-1) bits / symbol (AN-1 layer) (JN-1: integer), the interleave distance of an arbitrary layer Ag-1 is (layer Ag). -1 interleave distance -1) = (hierarchy Ag
A hierarchical transmission system characterized by a relationship of (1) × Jg (Jg: integer). 3. The method according to claim 1, wherein K bits per symbol are determined by soft decision.
A0 layer), K × J1 bit (A1 layer), K × J1 ×
J2 bit (A2 hierarchy) K × ΠJi (initial value i is 1 to
In a layer transmission system composed of N layers requiring quantization of (N-1) bits (AN-1 layer) (JN-1: integer), an interleave distance of an arbitrary layer Ag-1 is expressed by (layer Ag-1). Interleave distance -1) = (hierarchy Ag
Interleave distance-1) × Jg (Jg: integer). 4. The decoding apparatus according to claim 2, wherein said group forming means forms a set of Jg symbols as an input of deinterleaving of said arbitrary layer Ag-1. A decoding apparatus comprising: deinterleaving means for deinterleaving a set of Jg symbols as one unit; and output means for outputting the deinterleaved unit as one symbol by the means. 5. The decoding device according to claim 4, wherein said de-interleaving means is constituted by a memory circuit. 6. The encoding apparatus according to claim 2, wherein J is input as an interleave of said arbitrary layer Ag-1.
g symbol sets, interleaving means for interleaving the set Jg symbols as one unit, and output means for outputting the interleaved units as one symbol. Encoding device. 7. The decoding apparatus according to claim 6, wherein said interleaving means is constituted by a memory circuit. 8. An interleave apparatus, which performs interleave processing by grouping several symbols according to the interleave distance.