MXPA02002337A - Aparato de video, notablemente un descodificador de video, y proceso para control de memoria en tal aparato. - Google Patents

Aparato de video, notablemente un descodificador de video, y proceso para control de memoria en tal aparato.

Info

Publication number
MXPA02002337A
MXPA02002337A MXPA02002337A MXPA02002337A MXPA02002337A MX PA02002337 A MXPA02002337 A MX PA02002337A MX PA02002337 A MXPA02002337 A MX PA02002337A MX PA02002337 A MXPA02002337 A MX PA02002337A MX PA02002337 A MXPA02002337 A MX PA02002337A
Authority
MX
Mexico
Prior art keywords
video
memory
memory control
notably
video decoder
Prior art date
Application number
MXPA02002337A
Other languages
English (en)
Inventor
Ritz Eduard
Original Assignee
Thomson Licensing Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa filed Critical Thomson Licensing Sa
Publication of MXPA02002337A publication Critical patent/MXPA02002337A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4435—Memory management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Astronomy & Astrophysics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)
  • Bus Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La invencion se relaciona con un aparato de video con un descodificador (6) digital que tiene una primera memoria (8) sobre un enlace comun interno y unida a un circuito (12) OSD y a una segunda memoria (10) via un enlace comun principal, el aparato de video comprende un medio para llevar a cabo la transferencia de DMA entre la primera memoria (8) y la segunda memoria (10). La Invencion tambien propone un proceso para controlar tal aparato de video.
MXPA02002337A 2001-03-09 2002-03-04 Aparato de video, notablemente un descodificador de video, y proceso para control de memoria en tal aparato. MXPA02002337A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01400628A EP1239670A1 (en) 2001-03-09 2001-03-09 Video apparatus, notably video decoder, and process for memory control in such an apparatus

Publications (1)

Publication Number Publication Date
MXPA02002337A true MXPA02002337A (es) 2004-06-22

Family

ID=8182649

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA02002337A MXPA02002337A (es) 2001-03-09 2002-03-04 Aparato de video, notablemente un descodificador de video, y proceso para control de memoria en tal aparato.

Country Status (9)

Country Link
US (1) US7154559B2 (es)
EP (1) EP1239670A1 (es)
JP (1) JP3989752B2 (es)
KR (1) KR100852394B1 (es)
CN (1) CN1235159C (es)
AT (1) ATE368355T1 (es)
DE (1) DE60221306T2 (es)
ES (1) ES2290208T3 (es)
MX (1) MXPA02002337A (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080281999A1 (en) * 2007-05-07 2008-11-13 Mediatek Inc. Electronic system with direct memory access and method thereof
CN101640770B (zh) * 2008-08-18 2011-05-11 青岛海信信芯科技有限公司 屏幕显示菜单的数据载入方法和视频设备
CN101720040B (zh) * 2009-11-11 2011-05-11 四川长虹电器股份有限公司 融合高速存储器和dma通道的视频解码优化方法
CN102291549A (zh) * 2011-09-07 2011-12-21 天津天地伟业数码科技有限公司 基于cortex-m3的osd结构

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608459A (en) * 1993-08-13 1997-03-04 Texas Instruments Incorporated Video data decoder having motion compensation and image memory circuitry on single substrate
JP3301263B2 (ja) * 1995-03-29 2002-07-15 株式会社日立製作所 データ復号装置
DE69631393T2 (de) * 1995-03-29 2004-10-21 Hitachi Ltd Dekoder für komprimierte und multiplexierte Bild- und Audiodaten
JPH09128330A (ja) * 1995-11-06 1997-05-16 Sony Corp 映像表示装置
JPH1093928A (ja) * 1996-09-12 1998-04-10 Hitachi Ltd ディジタル放送デコーダ
KR19980042023A (ko) * 1996-11-01 1998-08-17 윌리엄비.켐플러 오디오 영상 시스템용 집적 회로
US6226291B1 (en) * 1996-11-01 2001-05-01 Texas Instruments Incorporated Transport stream packet parser system
US6369855B1 (en) * 1996-11-01 2002-04-09 Texas Instruments Incorporated Audio and video decoder circuit and system
JPH11103429A (ja) * 1997-09-29 1999-04-13 Sony Corp 画像データ復号化装置及びオン・スクリーン・ディスプレイ・データ更新方法
DE19918046B4 (de) * 1998-04-23 2007-02-15 Lg Electronics Inc. Speicherstruktur für Bild-in-Bild-Anzeige bei einer digitalen Videoanzeigeeinheit sowie Verfahren hierfür
US6085278A (en) * 1998-06-02 2000-07-04 Adaptec, Inc. Communications interface adapter for a computer system including posting of system interrupt status
US6593937B2 (en) * 1998-06-18 2003-07-15 Sony Corporation Method of and apparatus for handling high bandwidth on-screen-display graphics data over a distributed IEEE 1394 network utilizing an isochronous data transmission format
JP3356691B2 (ja) * 1998-07-07 2002-12-16 株式会社東芝 情報記録媒体とその記録方法及び再生方法
US6137539A (en) * 1998-10-09 2000-10-24 Matshushita Electric Industrial Co, Ltd Digital television status display
US6774918B1 (en) * 2000-06-28 2004-08-10 Koninklijke Philips Electronics N.V. Video overlay processor with reduced memory and bus performance requirements
JP3598515B2 (ja) * 2001-12-07 2004-12-08 船井電機株式会社 ディスク再生装置及びｏｓｄ画像の生成方法

Also Published As

Publication number Publication date
DE60221306D1 (de) 2007-09-06
KR20020072498A (ko) 2002-09-16
JP2002335466A (ja) 2002-11-22
CN1235159C (zh) 2006-01-04
US20020126225A1 (en) 2002-09-12
DE60221306T2 (de) 2008-04-10
JP3989752B2 (ja) 2007-10-10
ATE368355T1 (de) 2007-08-15
US7154559B2 (en) 2006-12-26
CN1374802A (zh) 2002-10-16
KR100852394B1 (ko) 2008-08-18
ES2290208T3 (es) 2008-02-16
EP1239670A1 (en) 2002-09-11

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