MXPA00006901A - Asynchronous memory card - Google Patents

Asynchronous memory card

Info

Publication number
MXPA00006901A
MXPA00006901A MXPA/A/2000/006901A MXPA00006901A MXPA00006901A MX PA00006901 A MXPA00006901 A MX PA00006901A MX PA00006901 A MXPA00006901 A MX PA00006901A MX PA00006901 A MXPA00006901 A MX PA00006901A
Authority
MX
Mexico
Prior art keywords
circuit
memory
code
reception
terminal
Prior art date
Application number
MXPA/A/2000/006901A
Other languages
Spanish (es)
Inventor
Pascal Cooreman
Stephane Rayon
Bertrand Gomez
Original Assignee
Gemplus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus filed Critical Gemplus
Publication of MXPA00006901A publication Critical patent/MXPA00006901A/en

Links

Abstract

The invention relates to contact memory cards (16) essentially comprising a memory (10) and its approach circuits (12, 14). The invention is characterized in that the approach circuits of the memory are modified (20) to allow for writing in or reading the memory (10) by means of electrical signals supplied by the terminal (18) in accordance with an asynchronous communication protocol with verification of the integrity of the transmitted codes. The signals received at the contacts (16) are analysed by the circuit (22) and then directed to the address register (26) and data register (28) by the switch circuit (24). The circuit (22) and the control circuit (14) transmit messages and codes to the terminal (18) by way of a transmission circuit (34).

Description

ASYNCHRONOUS MEMORY CARD DESCRIPTION OF THE INVENTION The invention relates to memory cards, ie to cards essentially comprising a memory and its address circuits for recording and reading data or information. The memory of these cards is recorded and / or read with the help of a terminal, such as a card reader, which communicates with the memory by electrical signals applied by means of contacts. The electrical signals are elaborated by the terminal following the particular normative protocols that have by peculiarity the being of synchronous type with indirect direction. With such protocols, the development of the transaction is as follows: - a zeroing of the card, mainly of the address address of the memory, or the putting under tension, either by a signal of zeroing on a spindle provided for this purpose; - a positioning of the memory address counter for good direction by applying a number of determined pulses on a spindle corresponding to the pulses of the clock; - a command or order to register or read in memory, by means of a combination of signals applied on an input / output spindle and on another spindle which can be the zero spindle, the clock spindle or any other spindle. The drawbacks of a memory card of this type that operates according to such an operation mode are summarized below. The communication between a reader and a card mainly for a 'financial transaction, being sensitive to electrical noises (low voltage, electrical contacts that fail, parasites, etc.), does not guarantee the accuracy of the messages exchanged. This mainly involves repeating the communication once or several times to ensure that the transaction is correctly carried out. - Repetition of messages increases the time needed for a transaction.
- In addition, it is possible to have erroneous transactions subsequent to these electrical noises. The address of the memory is carried out by means of a pulse counter that counts the series of pulses that are applied to it and the code announced by the counter at the end of this series constitutes the address code of the memory. This direction, called indirect, implies a certain duration of life when counting the impulses, and constitutes a source of error, for example if an impulse is not taken into account for various reasons. - No control of the integrity of the data or the order received is carried out, where there is an absence of security. - The transaction protocol is of the synchronous type, which implies a rigorous synchronism between the terminal and the memory card, which is sometimes difficult to obtain and maintain in the course of the transaction as a result of external disturbances. - No acknowledgment of receipt is made at the time of receipt of the data or the order received. - No verification of the good execution of the command is carried out.
An objective of the present invention is therefore to make a memory card that does not have the aforementioned drawbacks. This objective is achieved by modifying the signals applied to the memory card and the access circuits to the memory of the card, so that: - the communication between the terminal and the memory card is carried out according to an asynchronous communication protocol; - the address of the memory is carried out by direct address; - the information that is received by the card and related to an address, an order or a data item is verified; the memory card effects a reception acknowledgment for the terminal of the received information, and its integrity; - the memory card transmits to the terminal a good execution information of the order. The invention relates to a memory card with contacts comprising a memory adapted to cooperate with a terminal by means of access circuits comprising a steering circuit and a control circuit, characterized in that the access circuits to said memory also comprise : - a circuit for receiving and analyzing the electrical signals applied to the contacts of the memory card by the terminal, said reception and analysis circuit provides the messages and codes; - a circuit for interpreting and maneuvering the codes provided by the analysis circuit, whether it is an address code of the memory, a data code or an order or command code; - an address register that records the address code provided by the interpretation and maneuvering circuit for the provision of the address circuit; - at least one data record that registers the command code of the operation to be performed on the memory or the code of the data to be recorded if necessary, to put said codes at the disposal of the control circuit in order to perform the indicated operation by the command code, at least one output register that registers the code read in the memory or the execution status code of the command or command, provided by the control circuit, and - a transmission circuit for contacts of the codes provided by the output register, and the messages provided by the reception and analysis circuit for transmitting them to the terminal. The card according to the invention has the advantage by means of some minor supplementary operations, of more previously wired functions, of being fully compatible with the existing deposit readers. In particular, it is particularly advantageous to be able to use the microprocessor card readers, which is currently impossible with current memory cards. The invention will be better understood on reading the following description of a particular example of embodiment, said description being made in relation to the attached drawing in which the single figure is a functional diagram of a memory card according to the invention. A memory card 40 comprises, in a known manner: a memory 10 of the type allowing the reading and recording of data in the form of binary numbers in elementary cells, an address circuit 12 of the memory 10 for selecting one or more groups of elementary cells each corresponding to a data for reading or recording, - a control circuit 14 of the memory 10 and of the address circuit 12, for recording or reading the cells of the memory 10 to a direction indicated in the circuit of address 12, and - a plurality of contacts 16 placed on one of the sides of the card, to make the electrical connections between a terminal 18 and the memory card. According to the invention, the memory card comprises, in addition to the elements indicated above, a device 20 that makes the connection between, on the one hand, the plurality of contacts 16 and, on the other hand, the address circuit 12 and the circuit 14. This device 20 comprises: a reception and analysis circuit 22 for electrical signals received on the contacts 16, for analyzing the electrical signals and, on the one hand, providing the messages to the terminal 18 and, on the other hand, the representative data codes, addresses of memory and command cells or instructions to be made, - an interpretation and operation circuit 24 of the codes provided by the reception and analysis circuit 22, an address register 26 for recording the address code transmitted by the terminal and the provision of the address circuit 12, - at least one data record 28 for recording the code data code or the instruction code transmitted by the terminal and the provision of the control circuit 14, - at least one output register 32 for recording the code read in the memory 10 or the execution status of the instruction, and - a transmission circuit 34 of the code contained in the output register 32, to the terminal 16 by means of the contacts 16. The connection between the terminal 18 and the card 40 is effected by the plurality of contacts 16, applying on these contacts electrical signals that are regulated according to communication protocols called asynchronous. These protocols can be of different known types and mainly those known under the name RS232, in what concerns a serial connection commonly used between a computer called personal and its peripherals or the denominations V22, V23, etc., as regards to the connection by modem. The chosen protocol is put into operation by the terminal and must be comprised by the memory card at the level of the reception and analysis circuit 22. This last circuit 22 performs the reception of the electrical signals received from the terminal and the analysis is carried out to control integrity. For this purpose, the terminal is designed to add redundant information in the transmitted signals, information that the reception and analysis circuit 22 is able to verify the presence and the value. It can be the presence of a parity bit or a redundant cyclic code. It should be noted that numerous communication protocols provide such redundancy to verify the integrity of the information transmitted.
In the case where this verification is unsuccessful, the instruction is not executed. In addition to the absence of execution of the command or command, the reception and analysis circuit 22 is provided to provide the terminal with an acknowledgment such as a code indicating that the card has received the information well, and that its integrity it's correct. Otherwise, it provides an error code. Such acknowledgments of receipt or reception are provided in certain communication protocols. According to the invention, the address of the memory 10 is directly effected by an address code that is received and analyzed by the reception and analysis circuit 22. A direct address of this type can be performed by putting into operation a known protocol under the abbreviation I2C, protocol used for the piloting of computer peripherals. This address code is detected by the interpretation and maneuvering circuit 24 which transmits it to the address register 26. The interpretation and maneuvering circuit 24 also detects the data and instruction codes and transmits them to one or more registers 28, with the codes contained in the register 28 being placed at the disposal of the control circuit 14. When the instruction has been carried out, the control circuit 14 it is intended to generate a status code indicating the execution of the instruction or an error code indicating that the instruction has not been executed. This code is transmitted to the terminal 18 by means of the output register 32 which receives the code of the control circuit 14 and of the transmission circuit 34. When the instruction consists of a reading, the code read in the memory is transmitted to the terminal by means of the output register 32 and the transmission circuit 34. Of course, the output register 32 can be in the form of two registers, one for the status codes and the other for the data read in the memory 10. In the memory card that has just been described, the development of a transaction with a terminal is as follows: the terminal generates an instruction according to an application program adapted for the memory card according to the invention, L ^ CUUU. l ± J_ H, instruction, an address code and a data code, the set constitutes a message, - the terminal elaborates a redundancy information such as a parity digit or a redundant cyclic code, and introduces it into the message constituted of the codes to be transmitted, - the terminal transmits the codes to the memory card in asynchronous mode by means of the contacts 16, the reception and analysis circuit 22 validates the message received by the memory card, the reception circuit and of analysis 22 transmits an acknowledgment of receipt of the message to the terminal by means of the transmission circuit, indicating by a code the good or bad reception of the message, - the control circuit 14 executes the instruction, and - the control circuit 14 transmits to the terminal a message that attests to the execution or not of the instruction by means of the output register 32 and the transmission circuit 34.

Claims (7)

1. Memory card with contacts comprising a memory adapted to cooperate with a terminal, by means of access circuits comprising a steering circuit and a control circuit, characterized in that the access circuits to the memory also comprise: a circuit for receiving and analyzing the electrical signals applied to the contacts of the memory card by the terminal, said reception and analysis circuit provides the messages and the codes; - a circuit for interpreting and maneuvering the codes provided by the reception and analysis circuit, whether it is an address code of the memory, a data code or a command or instruction code; - an address register that records the address code provided by the interpretation and maneuvering circuit, for the provision of the address circuit; - at least one data record that registers the command code of the operation to be carried out on the memory, or the code of the data that must be registered, to put said codes at the disposition of the control circuit with a view to carrying out the operation indicated by the command code; - at least one output register that registers the code read in the memory or the execution status code of the command, provided by the control circuit, and - a transmission circuit for the contacts of the codes provided by the output register and the messages provided by the reception and analysis circuit for transmitting them to the terminal.
2. Memory card according to claim 1, characterized in that the reception and analysis circuit is adapted to exchange data according to an asynchronous communication protocol.
3. Memory card according to claim 1, characterized in that the reception and analysis circuit is adapted to exchange the data with the message integrity control corresponding to the transmitted electrical signals.
4. Memory card according to claim 1, characterized in that the reception and analysis circuit is adapted to detect and understand the electrical signals transmitted by the terminal, according to an asynchronous communication protocol with message integrity control corresponding to the electrical signals transmitted.
5. Memory card according to any of the preceding claims, characterized in that the transmission circuit is adapted to transmit the messages provided by the reception and analysis circuit and the codes provided by the output register in a form detectable and understandable by the terminal according to the asynchronous communication protocol.
6. Memory card according to any of the preceding claims, characterized in that the reception and analysis circuit is adapted to generate a signal indicating the correct and complete reception of the signals transmitted by the terminal, said signal being applied to a circuit of transmission.
7. Memory card according to any of the preceding claims, characterized in that the control circuit is adapted to generate a status code indicating the execution or not of the instruction.
MXPA/A/2000/006901A 1998-01-27 2000-07-13 Asynchronous memory card MXPA00006901A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR98/00859 1998-01-27

Publications (1)

Publication Number Publication Date
MXPA00006901A true MXPA00006901A (en) 2001-06-26

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