MX9706592A - Protocolo de coherencia para multiprocesamiento cache en un conducto local. - Google Patents

Protocolo de coherencia para multiprocesamiento cache en un conducto local.

Info

Publication number
MX9706592A
MX9706592A MX9706592A MX9706592A MX9706592A MX 9706592 A MX9706592 A MX 9706592A MX 9706592 A MX9706592 A MX 9706592A MX 9706592 A MX9706592 A MX 9706592A MX 9706592 A MX9706592 A MX 9706592A
Authority
MX
Mexico
Prior art keywords
cache
signal
asserts
local bus
memory
Prior art date
Application number
MX9706592A
Other languages
English (en)
Inventor
Ketan S Bhat
Gregory S Mathews
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of MX9706592A publication Critical patent/MX9706592A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un sistema de computadora que mantiene coherencia caché entre una pluralidad de dispositivos de almacenamiento en caché (210, 220) acoplado a través de un conducto local (200), incluye un maestro de conducto (270) una memoria (250), y una pluralidad de complejos caché (210, 220), todos acoplados al conducto local (200). Cuando el maestro de conducto (270) solicita una lectura o escritura con la memoria (250), los complejos caché (210, 220) husmean la transaccion. Cada complejo caché (210, 220) estima una señal de ocupado durante el proceso de husmeado. Un circuito de deteccion (260) detecta cuando las señales de ocupado se han desestimado y estima una señal de terminado. Si uno de los husmeados resulta en un acierto caché a una línea sucia, el complejo caché respectivo (210, 220) estima una señal sucia. Si uno de los husmeados resulta en un acierto caché a una línea limpia, el complejo caché respectivo estima una señal limpia. Si la memoria (250) detecta una estimacion simultánea de la señal sucia y la señal de terminado, detiene la solicitud de transaccion desde el maestro de conducto (270).
MX9706592A 1995-03-17 1996-03-15 Protocolo de coherencia para multiprocesamiento cache en un conducto local. MX9706592A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40615395A 1995-03-17 1995-03-17
PCT/US1996/003614 WO1996029653A1 (en) 1995-03-17 1996-03-15 Multi-processing cache coherency protocol on a local bus

Publications (1)

Publication Number Publication Date
MX9706592A true MX9706592A (es) 1997-11-29

Family

ID=23606754

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9706592A MX9706592A (es) 1995-03-17 1996-03-15 Protocolo de coherencia para multiprocesamiento cache en un conducto local.

Country Status (7)

Country Link
US (1) US5802577A (es)
EP (1) EP0815513B1 (es)
JP (1) JP3787155B2 (es)
AU (1) AU693334B2 (es)
DE (1) DE69636452T2 (es)
MX (1) MX9706592A (es)
WO (1) WO1996029653A1 (es)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5875469A (en) * 1996-08-26 1999-02-23 International Business Machines Corporation Apparatus and method of snooping processors and look-aside caches
JP3288261B2 (ja) * 1997-06-19 2002-06-04 甲府日本電気株式会社 キャッシュシステム
US6081876A (en) * 1997-09-22 2000-06-27 Hewlett-Packard Company Memory error containment in network cache environment via restricted access
US5983024A (en) * 1997-11-26 1999-11-09 Honeywell, Inc. Method and apparatus for robust data broadcast on a peripheral component interconnect bus
US6289419B1 (en) * 1998-03-06 2001-09-11 Sharp Kabushiki Kaisha Consistency control device merging updated memory blocks
US6308255B1 (en) * 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6480952B2 (en) 1998-05-26 2002-11-12 Advanced Micro Devices, Inc. Emulation coprocessor
US6192453B1 (en) * 1998-07-13 2001-02-20 International Business Machines Corporation Method and apparatus for executing unresolvable system bus operations
US6604162B1 (en) 2000-06-28 2003-08-05 Intel Corporation Snoop stall reduction on a microprocessor external bus
GB0028353D0 (en) * 2000-11-21 2001-01-03 Aspex Technology Ltd Improvements relating to digital data communications
JP2002342162A (ja) * 2001-05-14 2002-11-29 Nec Corp メモリアクセス制御方式及びホストブリッジ
US6799247B1 (en) * 2001-08-23 2004-09-28 Cisco Technology, Inc. Remote memory processor architecture
US6983348B2 (en) * 2002-01-24 2006-01-03 Intel Corporation Methods and apparatus for cache intervention
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US20040153611A1 (en) * 2003-02-04 2004-08-05 Sujat Jamil Methods and apparatus for detecting an address conflict
US7287126B2 (en) * 2003-07-30 2007-10-23 Intel Corporation Methods and apparatus for maintaining cache coherency
US8281079B2 (en) * 2004-01-13 2012-10-02 Hewlett-Packard Development Company, L.P. Multi-processor system receiving input from a pre-fetch buffer
US8301844B2 (en) * 2004-01-13 2012-10-30 Hewlett-Packard Development Company, L.P. Consistency evaluation of program execution across at least one memory barrier
US7383409B2 (en) 2004-01-13 2008-06-03 Hewlett-Packard Development Company, L.P. Cache systems and methods for employing speculative fills
US7409503B2 (en) * 2004-01-13 2008-08-05 Hewlett-Packard Development Company, L.P. Register file systems and methods for employing speculative fills
US7360069B2 (en) * 2004-01-13 2008-04-15 Hewlett-Packard Development Company, L.P. Systems and methods for executing across at least one memory barrier employing speculative fills
US7376794B2 (en) * 2004-01-13 2008-05-20 Hewlett-Packard Development Company, L.P. Coherent signal in a multi-processor system
US7409500B2 (en) * 2004-01-13 2008-08-05 Hewlett-Packard Development Company, L.P. Systems and methods for employing speculative fills
US7406565B2 (en) * 2004-01-13 2008-07-29 Hewlett-Packard Development Company, L.P. Multi-processor systems and methods for backup for non-coherent speculative fills
US7380107B2 (en) * 2004-01-13 2008-05-27 Hewlett-Packard Development Company, L.P. Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss
US7340565B2 (en) * 2004-01-13 2008-03-04 Hewlett-Packard Development Company, L.P. Source request arbitration
US7962696B2 (en) * 2004-01-15 2011-06-14 Hewlett-Packard Development Company, L.P. System and method for updating owner predictors
US7240165B2 (en) * 2004-01-15 2007-07-03 Hewlett-Packard Development Company, L.P. System and method for providing parallel data requests
US7856534B2 (en) 2004-01-15 2010-12-21 Hewlett-Packard Development Company, L.P. Transaction references for requests in a multi-processor network
US7395374B2 (en) * 2004-01-20 2008-07-01 Hewlett-Packard Company, L.P. System and method for conflict responses in a cache coherency protocol with ordering point migration
US7818391B2 (en) * 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
US20050160238A1 (en) * 2004-01-20 2005-07-21 Steely Simon C.Jr. System and method for conflict responses in a cache coherency protocol with ordering point migration
US7143245B2 (en) * 2004-01-20 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for read migratory optimization in a cache coherency protocol
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US8090914B2 (en) * 2004-01-20 2012-01-03 Hewlett-Packard Development Company, L.P. System and method for creating ordering points
US7620696B2 (en) * 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
US8176259B2 (en) * 2004-01-20 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for resolving transactions in a cache coherency protocol
US7769959B2 (en) * 2004-01-20 2010-08-03 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration to memory
US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
US7149852B2 (en) * 2004-01-20 2006-12-12 Hewlett Packard Development Company, Lp. System and method for blocking data responses
US7177987B2 (en) * 2004-01-20 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for responses between different cache coherency protocols
CN101065735A (zh) * 2004-11-24 2007-10-31 皇家飞利浦电子股份有限公司 本地存储器数据的一致性高速缓存
US9477600B2 (en) 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
DE4037332C2 (de) * 1990-11-23 1995-06-29 Siemens Nixdorf Inf Syst Verfahren zur Fehlerüberwachung der Datenkonsistenz in einem Datenverarbeitungssystem und Schaltungsanordnung zur Durchführung des Verfahrens
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5335335A (en) * 1991-08-30 1994-08-02 Compaq Computer Corporation Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
US5426765A (en) * 1991-08-30 1995-06-20 Compaq Computer Corporation Multiprocessor cache abitration
US5301298A (en) * 1991-10-11 1994-04-05 Intel Corporation Processor for multiple cache coherent protocols
US5485592A (en) * 1992-04-07 1996-01-16 Video Technology Computers, Ltd. Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory

Also Published As

Publication number Publication date
EP0815513A1 (en) 1998-01-07
EP0815513A4 (en) 1999-08-04
EP0815513B1 (en) 2006-08-16
JPH11502345A (ja) 1999-02-23
AU693334B2 (en) 1998-06-25
JP3787155B2 (ja) 2006-06-21
AU5094696A (en) 1996-10-08
US5802577A (en) 1998-09-01
DE69636452D1 (de) 2006-09-28
DE69636452T2 (de) 2007-03-29
WO1996029653A1 (en) 1996-09-26

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