MX9504236A - Metodo y aparato para memoria de acceso aleatorio dinamica (dram) que provee ancho de banda de datos y rango de direccionamiento aumentados para dispositivos dram actuales y/o ancho de banda y rango de direccionamiento equivalentes para dispositivos. - Google Patents

Metodo y aparato para memoria de acceso aleatorio dinamica (dram) que provee ancho de banda de datos y rango de direccionamiento aumentados para dispositivos dram actuales y/o ancho de banda y rango de direccionamiento equivalentes para dispositivos.

Info

Publication number
MX9504236A
MX9504236A MX9504236A MX9504236A MX9504236A MX 9504236 A MX9504236 A MX 9504236A MX 9504236 A MX9504236 A MX 9504236A MX 9504236 A MX9504236 A MX 9504236A MX 9504236 A MX9504236 A MX 9504236A
Authority
MX
Mexico
Prior art keywords
band width
addressing range
dram
dram devices
dynamic random
Prior art date
Application number
MX9504236A
Other languages
English (en)
Inventor
Mukesh Chatter
Original Assignee
Mukesh Chatter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mukesh Chatter filed Critical Mukesh Chatter
Publication of MX9504236A publication Critical patent/MX9504236A/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

Un método y un aparato para mejorar la capacidad de acceso de dispositivos de memoria de acceso aleatorio dinámica asíncronos y síncronos por un nuevo procedimiento de interconexion y acceso en el cual se usan las mismas patas para el acceso a fila, columna y datos y en ambos ciclos de escritura y lectura; esto permite un aumento efectivo del ancho de banda de datos y el rango de direccionamiento en empaques del mismo tamaño y numero de patas substancialmente que las DRAMs actuales, o provee un desempeño equivalente en empaques más pequeños con menos patas. Esto permite reducir el numero de componentes requeridos para la misma configuracion, y provee densidad compatible en empaques más pequeños, y con un consumo de energía más bajo y una granularidad más fina y compatibilidad en las patas para un rango amplio de las DRAMs actuales.
MX9504236A 1994-10-07 1995-10-06 Metodo y aparato para memoria de acceso aleatorio dinamica (dram) que provee ancho de banda de datos y rango de direccionamiento aumentados para dispositivos dram actuales y/o ancho de banda y rango de direccionamiento equivalentes para dispositivos. MX9504236A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/320,058 US5590078A (en) 1994-10-07 1994-10-07 Method of and apparatus for improved dynamic random access memory (DRAM) providing increased data bandwidth and addressing range for current DRAM devices and/or equivalent bandwidth and addressing range for smaller DRAM devices

Publications (1)

Publication Number Publication Date
MX9504236A true MX9504236A (es) 1997-04-30

Family

ID=23244694

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9504236A MX9504236A (es) 1994-10-07 1995-10-06 Metodo y aparato para memoria de acceso aleatorio dinamica (dram) que provee ancho de banda de datos y rango de direccionamiento aumentados para dispositivos dram actuales y/o ancho de banda y rango de direccionamiento equivalentes para dispositivos.

Country Status (8)

Country Link
US (1) US5590078A (es)
EP (1) EP0706186A3 (es)
JP (1) JPH08315565A (es)
KR (1) KR960015576A (es)
CN (1) CN1152780A (es)
CA (1) CA2159953A1 (es)
MX (1) MX9504236A (es)
TW (1) TW288202B (es)

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US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US6199142B1 (en) * 1996-07-01 2001-03-06 Sun Microsystems, Inc. Processor/memory device with integrated CPU, main memory, and full width cache and associated method
US6031767A (en) * 1996-09-18 2000-02-29 International Business Machines Corporation Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information
US6327640B1 (en) 1997-03-07 2001-12-04 Advanced Micro Devices, Inc. Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller
US6016537A (en) * 1997-03-07 2000-01-18 Advanced Micro Devices, Inc. Method and apparatus for address multiplexing to support variable DRAM sizes
US6260101B1 (en) 1997-03-07 2001-07-10 Advanced Micro Devices, Inc. Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices
US7566478B2 (en) 2001-07-25 2009-07-28 Nantero, Inc. Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles
US6574130B2 (en) 2001-07-25 2003-06-03 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US6919592B2 (en) 2001-07-25 2005-07-19 Nantero, Inc. Electromechanical memory array using nanotube ribbons and method for making same
US6924538B2 (en) 2001-07-25 2005-08-02 Nantero, Inc. Devices having vertically-disposed nanofabric articles and methods of making the same
US6835591B2 (en) 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
US7259410B2 (en) 2001-07-25 2007-08-21 Nantero, Inc. Devices having horizontally-disposed nanofabric articles and methods of making the same
US6911682B2 (en) 2001-12-28 2005-06-28 Nantero, Inc. Electromechanical three-trace junction devices
US6643165B2 (en) 2001-07-25 2003-11-04 Nantero, Inc. Electromechanical memory having cell selection circuitry constructed with nanotube technology
US6706402B2 (en) 2001-07-25 2004-03-16 Nantero, Inc. Nanotube films and articles
US6784028B2 (en) 2001-12-28 2004-08-31 Nantero, Inc. Methods of making electromechanical three-trace junction devices
US7176505B2 (en) 2001-12-28 2007-02-13 Nantero, Inc. Electromechanical three-trace junction devices
KR100878231B1 (ko) * 2002-02-08 2009-01-13 삼성전자주식회사 액정 표시 장치 및 그 구동 방법과 프레임 메모리
US7335395B2 (en) 2002-04-23 2008-02-26 Nantero, Inc. Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
US7466160B2 (en) * 2002-11-27 2008-12-16 Inapac Technology, Inc. Shared memory bus architecture for system with processor and memory units
US7560136B2 (en) 2003-01-13 2009-07-14 Nantero, Inc. Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
CN100343822C (zh) * 2003-10-27 2007-10-17 华为技术有限公司 地址复用逻辑实现与sdram兼容的方法
CN100343823C (zh) * 2003-10-27 2007-10-17 华为技术有限公司 地址复用逻辑兼容多种sdram的方法
CN100343824C (zh) * 2003-11-07 2007-10-17 华为技术有限公司 一种实现sdram兼容设计的方法
US7965530B2 (en) * 2005-05-21 2011-06-21 Samsung Electronics Co., Ltd. Memory modules and memory systems having the same
KR101048380B1 (ko) * 2005-05-21 2011-07-12 삼성전자주식회사 메모리 모듈 장치
KR100719149B1 (ko) * 2005-09-28 2007-05-18 주식회사 하이닉스반도체 신호 정렬 회로 및 이를 구비한 반도체 메모리 소자
US7804723B2 (en) 2005-09-28 2010-09-28 Hynix Semiconductor Inc. Semiconductor memory device with signal aligning circuit
WO2007130640A2 (en) * 2006-05-04 2007-11-15 Inapac Technology, Inc. Memory device including multiplexed inputs
US7466603B2 (en) * 2006-10-03 2008-12-16 Inapac Technology, Inc. Memory accessing circuit system
US8462561B2 (en) * 2011-08-03 2013-06-11 Hamilton Sundstrand Corporation System and method for interfacing burst mode devices and page mode devices
CN105788027B (zh) * 2016-03-17 2019-12-17 中车株洲电力机车有限公司 一种事件记录装置及其记录方法
CN111045965B (zh) * 2019-10-25 2021-06-04 南京大学 一种多通道无冲突拆分的硬件实现方法及运行该方法的计算机设备与可读存储介质

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Also Published As

Publication number Publication date
TW288202B (es) 1996-10-11
US5590078A (en) 1996-12-31
CN1152780A (zh) 1997-06-25
KR960015576A (ko) 1996-05-22
JPH08315565A (ja) 1996-11-29
EP0706186A2 (en) 1996-04-10
EP0706186A3 (en) 1997-08-20
CA2159953A1 (en) 1996-04-08

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