MX9207530A - Apatao para recibir y decodificar un paquete de datos serial que contiene el estado de una red de dispositivos de entrada/salida de punto sencillo. - Google Patents

Apatao para recibir y decodificar un paquete de datos serial que contiene el estado de una red de dispositivos de entrada/salida de punto sencillo.

Info

Publication number
MX9207530A
MX9207530A MX9207530A MX9207530A MX9207530A MX 9207530 A MX9207530 A MX 9207530A MX 9207530 A MX9207530 A MX 9207530A MX 9207530 A MX9207530 A MX 9207530A MX 9207530 A MX9207530 A MX 9207530A
Authority
MX
Mexico
Prior art keywords
network
decode
receive
package
state
Prior art date
Application number
MX9207530A
Other languages
English (en)
Inventor
Paul Robert Buda
Kelvin Peele
Original Assignee
Square D Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Square D Co filed Critical Square D Co
Publication of MX9207530A publication Critical patent/MX9207530A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Abstract

Un sistema de comunicaciones entre un dispositivo a base de microprocesador y una red de una pluralidad de módulos repetidores remotos de entrada/salida, usa un protocolo de comunicaciones serial, sincrónico. El dispositivo a base de microprocesador ontiene un módulo transmisor para generar un paquete de datos que contiene el estado del dispositivo de salida conectado a los módulos repetidores remotos de entrada/salida acoplados a la red.
MX9207530A 1991-12-23 1992-12-23 Apatao para recibir y decodificar un paquete de datos serial que contiene el estado de una red de dispositivos de entrada/salida de punto sencillo. MX9207530A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/811,722 US5311508A (en) 1991-12-23 1991-12-23 Apparatus for receiving and decoding a serial data packet containing the status of a network of single point I/O devices

Publications (1)

Publication Number Publication Date
MX9207530A true MX9207530A (es) 1994-06-30

Family

ID=25207372

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9207530A MX9207530A (es) 1991-12-23 1992-12-23 Apatao para recibir y decodificar un paquete de datos serial que contiene el estado de una red de dispositivos de entrada/salida de punto sencillo.

Country Status (7)

Country Link
US (1) US5311508A (es)
EP (1) EP0619061A4 (es)
JP (1) JPH07502869A (es)
AU (1) AU658548B2 (es)
CA (1) CA2125704C (es)
MX (1) MX9207530A (es)
WO (1) WO1993013633A1 (es)

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US5608662A (en) * 1995-01-12 1997-03-04 Television Computer, Inc. Packet filter engine
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US5793750A (en) * 1995-10-20 1998-08-11 Schweitzer Engineering Laboratories, Inc. System of communicating output function status indications between two or more power system protective relays
US5777874A (en) * 1996-02-12 1998-07-07 Allen-Bradley Company, Inc. Programmable controller backup system
US5802321A (en) * 1996-06-20 1998-09-01 Square D Company Synchronous serial communication network for controlling single point I/O devices
US6233671B1 (en) 1998-03-31 2001-05-15 Intel Corporation Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6230257B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6192467B1 (en) 1998-03-31 2001-02-20 Intel Corporation Executing partial-width packed data instructions
US20070228144A1 (en) * 2000-08-01 2007-10-04 Lee Knackstedt Processing transactions using a register portion to track transactions
US7701683B2 (en) * 2001-07-06 2010-04-20 Schweitzer Engineering Laboratories, Inc. Apparatus, system, and method for sharing output contacts across multiple relays
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
US7321588B2 (en) * 2002-09-16 2008-01-22 M/A-Com, Inc. Serial control of radio frequency integrated circuits
US7065593B2 (en) * 2003-12-17 2006-06-20 Tellabs Petaluma, Inc. Centralized, double bandwidth, directional, shared bus communication system architecture
JP4264024B2 (ja) * 2004-04-21 2009-05-13 日本ギア工業株式会社 弁の開閉検査方法とその装置
US7860874B2 (en) * 2004-06-08 2010-12-28 Siemens Industry, Inc. Method for searching across a PLC network
US7512593B2 (en) * 2004-06-08 2009-03-31 Siemens Energy & Automation, Inc. System for searching across a PLC network
WO2007057014A1 (en) * 2005-11-15 2007-05-24 Linak A/S A communications method, in particular for hospital and nursing beds
US9256232B2 (en) 2009-06-12 2016-02-09 Schweitzer Engineering Laboratories, Inc. Voltage regulation using multiple voltage regulator controllers
US8427131B2 (en) * 2009-06-12 2013-04-23 Schweitzer Engineering Laboratories Inc Voltage regulation at a remote location using measurements from a remote metering device
US8476874B2 (en) * 2009-10-13 2013-07-02 Schweitzer Engineering Laboratories, Inc Systems and methods for synchronized control of electrical power system voltage profiles
CN111665778B (zh) * 2020-05-29 2022-05-24 国电南瑞科技股份有限公司 一种plc控制器与上位机快速通讯传输和数据处理的方法
CN112953680B (zh) * 2021-02-10 2022-12-23 Tcl华星光电技术有限公司 编码方法、解码方法、编码装置及解码装置

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Publication number Priority date Publication date Assignee Title
AT335005B (de) * 1975-01-22 1977-02-25 Leinfellner Helmut Ing Fehlererkennendes ubertragungssystem fur informationen mittels impulszugen vorgegebener lange
DE2522905C3 (de) * 1975-05-23 1978-03-09 Robert Bosch Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zur Erkennung von Übertragungsfehlern in einem Bi-Phase-codierten Datensignal
GB2094108A (en) * 1981-01-30 1982-09-08 Eltra Corp Method and apparatus for synchronizing a station connected in a data line
DE3144263A1 (de) 1981-11-07 1983-05-19 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Demodulations- und fehlererkennungsschaltung fuer ein biphase-signal
AU568977B2 (en) * 1985-05-10 1988-01-14 Tandem Computers Inc. Dual processor error detection system
KR900701112A (ko) * 1988-02-29 1990-08-17 기따다 데쯔야 직렬제어장치 및 그 제어방법
JPH0813057B2 (ja) * 1989-02-03 1996-02-07 日本電気株式会社 Ｈｄｌｃ可変長パケットと非ｈｄｌｃ固定長パケットとの混在転送方法
AU664413B2 (en) 1991-12-23 1995-11-16 Square D Company A synchronous serial communication network for controlling single point I/O devices
US5283781A (en) 1991-12-23 1994-02-01 Square D Company Apparatus for receiving and modifying a serial data packet from a communications network to indicate its status
US5287353A (en) * 1991-12-23 1994-02-15 Square D Company Apparatus for generating and sending a serial data packet for controlling a network of single point I/O devices

Also Published As

Publication number Publication date
EP0619061A1 (en) 1994-10-12
CA2125704C (en) 1999-01-26
JPH07502869A (ja) 1995-03-23
AU3423993A (en) 1993-07-28
CA2125704A1 (en) 1993-07-08
WO1993013633A1 (en) 1993-07-08
EP0619061A4 (en) 1996-01-31
AU658548B2 (en) 1995-04-13
US5311508A (en) 1994-05-10

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