MX384239B - Correccion de error de enlace en sistema de memoria. - Google Patents

Correccion de error de enlace en sistema de memoria.

Info

Publication number
MX384239B
MX384239B MX2019002194A MX2019002194A MX384239B MX 384239 B MX384239 B MX 384239B MX 2019002194 A MX2019002194 A MX 2019002194A MX 2019002194 A MX2019002194 A MX 2019002194A MX 384239 B MX384239 B MX 384239B
Authority
MX
Mexico
Prior art keywords
link error
increasing
memory
error correction
memory system
Prior art date
Application number
MX2019002194A
Other languages
English (en)
Other versions
MX2019002194A (es
Inventor
Jungwon Suh
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2019002194A publication Critical patent/MX2019002194A/es
Publication of MX384239B publication Critical patent/MX384239B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Probability & Statistics with Applications (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Memory System (AREA)

Abstract

Técnicas convencionales de corrección de error de enlace en subsistemas de memoria incluyen ya sea el ensanchamiento de la anchura I/O o el incremento de la longitud de ráfaga; no obstante, ambas técnicas tienen inconvenientes; en uno o más aspectos, se propone incorporar corrección de error de enlace en el huésped y los dispositivos de memoria para corregir los inconvenientes asociados con las técnicas convencionales; el subsistema de memoria propuesto es conveniente ya que se puede mantener la arquitectura de interfaz de los sistemas de memoria convencionales; también, la corrección de error de enlace tiene la capacidad para ser proporcionada con el subsistema de memoria propuesto sin incrementar la anchura de I/O y sin incrementar la longitud de la ráfaga.
MX2019002194A 2016-08-26 2017-07-07 Correccion de error de enlace en sistema de memoria. MX384239B (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662380104P 2016-08-26 2016-08-26
US15/643,455 US10331517B2 (en) 2016-08-26 2017-07-06 Link error correction in memory system
PCT/US2017/041129 WO2018038813A1 (en) 2016-08-26 2017-07-07 Link error correction in memory system

Publications (2)

Publication Number Publication Date
MX2019002194A MX2019002194A (es) 2019-06-24
MX384239B true MX384239B (es) 2025-03-14

Family

ID=61242685

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2019002194A MX384239B (es) 2016-08-26 2017-07-07 Correccion de error de enlace en sistema de memoria.

Country Status (20)

Country Link
US (1) US10331517B2 (es)
EP (1) EP3479241B1 (es)
JP (1) JP6630869B2 (es)
KR (1) KR102045712B1 (es)
CN (1) CN109643257B (es)
AU (2) AU2017315303B2 (es)
BR (1) BR112019003473A2 (es)
CA (1) CA3032278C (es)
CO (1) CO2019001630A2 (es)
ES (1) ES2829331T3 (es)
IL (1) IL264303B (es)
MX (1) MX384239B (es)
MY (1) MY201067A (es)
PH (1) PH12019500160A1 (es)
RU (1) RU2710977C1 (es)
SA (1) SA519401035B1 (es)
SG (1) SG11201900375YA (es)
TW (1) TWI684102B (es)
WO (1) WO2018038813A1 (es)
ZA (1) ZA201901194B (es)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039086B (zh) * 2017-05-17 2024-08-30 西安紫光国芯半导体有限公司 具有兼容不同数据长度的纠错功能的存储器和纠错方法
US10387242B2 (en) 2017-08-21 2019-08-20 Qualcomm Incorporated Dynamic link error protection in memory systems
US10725912B2 (en) 2018-12-19 2020-07-28 Micron Technology, Inc. Power loss protection in memory sub-systems
US11537464B2 (en) 2019-06-14 2022-12-27 Micron Technology, Inc. Host-based error correction
US11372717B2 (en) * 2019-08-30 2022-06-28 Qualcomm Incorporated Memory with system ECC
US11210167B2 (en) * 2019-10-28 2021-12-28 Intel Corporation Memory wordline isolation for improvement in reliability, availability, and scalability (RAS)
CN110750406B (zh) * 2019-10-29 2023-10-31 湖南国科微电子股份有限公司 一种检测方法、装置和soc芯片
US11493949B2 (en) * 2020-03-27 2022-11-08 Qualcomm Incorporated Clocking scheme to receive data
US11728003B2 (en) 2020-05-12 2023-08-15 Qualcomm Incorporated System and memory with configurable error-correction code (ECC) data protection and related methods
US11157359B2 (en) * 2020-09-24 2021-10-26 Intel Corporation Techniques to implement a hybrid error correction code scheme
KR20230021409A (ko) 2021-08-05 2023-02-14 에스케이하이닉스 주식회사 트레이닝동작을 수행하기 위한 반도체시스템
US11687273B2 (en) * 2021-09-29 2023-06-27 Micron Technology, Inc. Memory controller for managing data and error information
CN114006819A (zh) * 2021-11-03 2022-02-01 北京天融信网络安全技术有限公司 一种检测策略生成及装置、数据传输方法及装置
US12073901B2 (en) 2021-11-30 2024-08-27 Qualcomm Incorporated Hybrid memory system with increased bandwidth
CN114171104A (zh) * 2021-12-17 2022-03-11 杨孟林 一种基于闪存的存储服务器在线修复系统
US12159033B2 (en) * 2022-10-18 2024-12-03 Qualcomm Incorporated Metadata registers for a memory device

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR9606294B1 (pt) * 1995-04-03 2009-01-13 mÉtodo para dispor dados de paridade, mÉtodo para transmitir, receber, gravar e reproduzir dados de informaÇço e dados de paridade, aparelho para dispor dados de paridade, sistema de transmissço de dados, transmissor de dados, receptor de dados, aparelho de gravaÇço e reproduÇço de dados, gravador de dados, reprodutor de dados, meio de gravaÇço e sinal tendo uma estrutura de dados de dados de informaÇço e dados de paridade.
US7032056B2 (en) * 2003-05-08 2006-04-18 International Business Machines Corporation Encoding of message onto strobe signals
KR100978268B1 (ko) * 2004-07-15 2010-08-26 엘에스산전 주식회사 분산 제어 시스템의 고속 이중화 데이터 복사 보드
KR100755371B1 (ko) 2005-05-03 2007-09-04 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 스트로우브 신호발생방법
CN101060015A (zh) * 2007-05-23 2007-10-24 北京芯技佳易微电子科技有限公司 一种多比特闪存及其错误检测和纠正的方法
EP2223301A4 (en) 2007-12-21 2012-04-04 Mosaid Technologies Inc NON-VOLATILE SEMICONDUCTOR ARRANGEMENT WITH POWER SAVING FEATURE
US8255783B2 (en) 2008-04-23 2012-08-28 International Business Machines Corporation Apparatus, system and method for providing error protection for data-masking bits
US8341498B2 (en) * 2010-10-01 2012-12-25 Sandisk Technologies Inc. System and method of data encoding
US8707133B2 (en) * 2011-12-05 2014-04-22 Lsi Corporation Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port
CN102546755A (zh) * 2011-12-12 2012-07-04 华中科技大学 云存储系统的数据存储方法
US8990670B2 (en) * 2012-09-28 2015-03-24 Intel Corporation Endurance aware error-correcting code (ECC) protection for non-volatile memories
US9064606B2 (en) 2012-12-20 2015-06-23 Advanced Micro Devices, Inc. Memory interface supporting both ECC and per-byte data masking
US9164834B2 (en) * 2013-05-06 2015-10-20 Samsung Electronics Co., Ltd. Semiconductor memory devices, memory systems including the same and method of writing data in the same
CN105468292B (zh) * 2014-09-05 2019-04-23 群联电子股份有限公司 数据存取方法、存储器储存装置及存储器控制电路单元
US9558066B2 (en) * 2014-09-26 2017-01-31 Intel Corporation Exchanging ECC metadata between memory and host system
KR102438552B1 (ko) * 2015-02-04 2022-09-01 에스케이하이닉스 주식회사 메모리 시스템 및 그 동작방법
US9965352B2 (en) * 2015-11-20 2018-05-08 Qualcomm Incorporated Separate link and array error correction in a memory system
US20180059976A1 (en) * 2016-08-26 2018-03-01 Sandisk Technologies Llc Storage System with Integrated Components and Method for Use Therewith

Also Published As

Publication number Publication date
PH12019500160A1 (en) 2019-11-11
MX2019002194A (es) 2019-06-24
AU2017315303A1 (en) 2019-02-07
JP2019525356A (ja) 2019-09-05
ZA201901194B (en) 2020-12-23
SA519401035B1 (ar) 2021-11-06
TW201810056A (zh) 2018-03-16
MY201067A (en) 2024-02-01
KR102045712B1 (ko) 2019-11-15
CO2019001630A2 (es) 2019-05-10
JP6630869B2 (ja) 2020-01-15
KR20190043540A (ko) 2019-04-26
EP3479241A1 (en) 2019-05-08
AU2019222960A1 (en) 2019-09-26
EP3479241B1 (en) 2020-08-19
AU2019222960B2 (en) 2020-10-15
NZ750205A (en) 2020-10-30
BR112019003473A2 (pt) 2019-05-21
IL264303B (en) 2019-08-29
US10331517B2 (en) 2019-06-25
IL264303A (en) 2019-02-28
SG11201900375YA (en) 2019-03-28
CA3032278A1 (en) 2018-03-01
CN109643257B (zh) 2020-07-03
RU2710977C1 (ru) 2020-01-14
CN109643257A (zh) 2019-04-16
AU2017315303B2 (en) 2020-06-18
US20180060171A1 (en) 2018-03-01
ES2829331T3 (es) 2021-05-31
WO2018038813A1 (en) 2018-03-01
TWI684102B (zh) 2020-02-01
CA3032278C (en) 2021-01-12

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