MX2016003229A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents
Dispositivo de procesamiento de datos y metodo de procesamiento de datos.Info
- Publication number
- MX2016003229A MX2016003229A MX2016003229A MX2016003229A MX2016003229A MX 2016003229 A MX2016003229 A MX 2016003229A MX 2016003229 A MX2016003229 A MX 2016003229A MX 2016003229 A MX2016003229 A MX 2016003229A MX 2016003229 A MX2016003229 A MX 2016003229A
- Authority
- MX
- Mexico
- Prior art keywords
- parity
- data processing
- ldpc
- bits
- matrix
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Pure & Applied Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
Abstract
La tecnología presente se relaciona con un dispositivo de procesamiento de datos y a un método de procesamiento de datos de modo que el código LDPC es proporcionado con una buena velocidad de error de bits. Un codificador LDPC codificado por un código LDPC cuya longitud de código es de 16200 bits y una velocidad es de 10/15. El código LDCP incluye los bits de información y los bits de paridad. Una matriz H de comprobación o verificación de paridad incluye una parte de la matriz de información que corresponde a los bits de información del código LDPC y una parte de la matriz de paridad que corresponde a los bits de paridad. La parte de la matriz de información de la matriz H de comprobación de paridad es representada por una tabla de valor inicial de la matriz de comprobación de paridad indicando la posición de un elemento 1 de la parte de la matriz de información para cada una de las 360 columnas. La tecnología presente es aplicable a un caso en el cual la codificación LDPC y la decodificación LDPC son realizadas.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013196090 | 2013-09-20 | ||
PCT/JP2014/073469 WO2015041074A1 (ja) | 2013-09-20 | 2014-09-05 | データ処理装置、及びデータ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
MX2016003229A true MX2016003229A (es) | 2016-06-07 |
MX369485B MX369485B (es) | 2019-11-11 |
Family
ID=52688725
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2016003229A MX369485B (es) | 2013-09-20 | 2014-09-05 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
MX2019013223A MX2019013223A (es) | 2013-09-20 | 2016-03-11 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2019013223A MX2019013223A (es) | 2013-09-20 | 2016-03-11 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
Country Status (8)
Country | Link |
---|---|
US (2) | US10277257B2 (es) |
EP (1) | EP3048734B1 (es) |
JP (1) | JP6364417B2 (es) |
KR (3) | KR102113943B1 (es) |
CN (1) | CN105531935B (es) |
CA (1) | CA2923596C (es) |
MX (2) | MX369485B (es) |
WO (1) | WO2015041074A1 (es) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015041074A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015178210A1 (ja) * | 2014-05-21 | 2015-11-26 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
CA2948600C (en) | 2014-05-21 | 2022-11-29 | Sony Corporation | Data processing device and method for decreasing the signal-to-noise power ratio per symbol for a selected bit error rate of a digital television broadcasting signal |
US20160336968A1 (en) * | 2015-05-11 | 2016-11-17 | Comtech Ef Data Corp. | System and method for encoding and decoding using a plurality of constellations within a single fec block |
WO2018168428A1 (ja) * | 2017-03-13 | 2018-09-20 | ソニーセミコンダクタソリューションズ株式会社 | 送信装置及び送信方法、受信装置及び受信方法、並びに、プログラム |
JP6912648B2 (ja) * | 2017-07-07 | 2021-08-04 | クアルコム,インコーポレイテッド | 低密度パリティ検査コードのベースグラフ選択を適用する通信技法 |
KR102389035B1 (ko) * | 2017-12-06 | 2022-04-22 | 한국전자통신연구원 | 압축 데이터 송수신 방법 및 이를 위한 장치 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4224777B2 (ja) | 2003-05-13 | 2009-02-18 | ソニー株式会社 | 復号方法および復号装置、並びにプログラム |
CN1902828B (zh) | 2003-08-08 | 2012-02-29 | 英特尔公司 | 用于改变低密度奇偶校验码字长度的方法和装置 |
JP4688841B2 (ja) * | 2007-03-20 | 2011-05-25 | 日本放送協会 | 符号化器及び復号器、並びに送信装置及び受信装置 |
TWI410055B (zh) * | 2007-11-26 | 2013-09-21 | Sony Corp | Data processing device, data processing method and program product for performing data processing method on computer |
MY155083A (en) * | 2007-11-26 | 2015-08-28 | Sony Corp | Data processing apparatus and data processing method as well as encoding apparatus and encoding method |
TWI497920B (zh) | 2007-11-26 | 2015-08-21 | Sony Corp | Data processing device and data processing method |
EP2091156B1 (en) | 2008-02-18 | 2013-08-28 | Samsung Electronics Co., Ltd. | Apparatus and method for channel encoding and decoding in a communication system using low-density parity-check codes |
JP2011176645A (ja) | 2010-02-24 | 2011-09-08 | Sony Corp | データ処理装置、及びデータ処理方法 |
JP2011176783A (ja) | 2010-02-26 | 2011-09-08 | Sony Corp | データ処理装置、及びデータ処理方法 |
JP5500379B2 (ja) | 2010-09-03 | 2014-05-21 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP5630278B2 (ja) * | 2010-12-28 | 2014-11-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP2012235269A (ja) | 2011-04-28 | 2012-11-29 | Sony Corp | データ処理装置、及び、データ処理方法 |
JP5664919B2 (ja) | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2560311A1 (en) | 2011-08-17 | 2013-02-20 | Panasonic Corporation | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
WO2015041074A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
CN105594130A (zh) | 2013-09-26 | 2016-05-18 | 索尼公司 | 数据处理装置和数据处理方法 |
US9735809B2 (en) * | 2013-09-26 | 2017-08-15 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
US20160233889A1 (en) * | 2013-09-26 | 2016-08-11 | Sony Corporation | Data processing device and data processing method |
WO2015045899A1 (ja) * | 2013-09-26 | 2015-04-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US9577679B2 (en) * | 2013-10-04 | 2017-02-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
US9871621B2 (en) * | 2013-10-30 | 2018-01-16 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
WO2015178210A1 (ja) * | 2014-05-21 | 2015-11-26 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
CA2948600C (en) * | 2014-05-21 | 2022-11-29 | Sony Corporation | Data processing device and method for decreasing the signal-to-noise power ratio per symbol for a selected bit error rate of a digital television broadcasting signal |
EP3148087B1 (en) * | 2014-05-21 | 2021-03-03 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 12/15 ldpc code of length 16200 |
-
2014
- 2014-09-05 WO PCT/JP2014/073469 patent/WO2015041074A1/ja active Application Filing
- 2014-09-05 MX MX2016003229A patent/MX369485B/es active IP Right Grant
- 2014-09-05 EP EP14845759.1A patent/EP3048734B1/en active Active
- 2014-09-05 CA CA2923596A patent/CA2923596C/en active Active
- 2014-09-05 US US14/913,870 patent/US10277257B2/en active Active
- 2014-09-05 JP JP2015537644A patent/JP6364417B2/ja active Active
- 2014-09-05 KR KR1020187035724A patent/KR102113943B1/ko active IP Right Grant
- 2014-09-05 KR KR1020177017244A patent/KR101929296B1/ko active IP Right Grant
- 2014-09-05 KR KR1020167003085A patent/KR101752331B1/ko active IP Right Grant
- 2014-09-05 CN CN201480050423.2A patent/CN105531935B/zh active Active
-
2016
- 2016-03-11 MX MX2019013223A patent/MX2019013223A/es unknown
-
2019
- 2019-03-13 US US16/352,175 patent/US10951241B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR101929296B1 (ko) | 2018-12-17 |
MX2019013223A (es) | 2020-01-15 |
US10951241B2 (en) | 2021-03-16 |
KR20160060028A (ko) | 2016-05-27 |
CA2923596A1 (en) | 2015-03-26 |
CN105531935B (zh) | 2020-03-31 |
CN105531935A (zh) | 2016-04-27 |
US20160204806A1 (en) | 2016-07-14 |
US20190215020A1 (en) | 2019-07-11 |
KR101752331B1 (ko) | 2017-06-29 |
CA2923596C (en) | 2021-03-30 |
KR102113943B1 (ko) | 2020-05-21 |
MX369485B (es) | 2019-11-11 |
EP3048734B1 (en) | 2019-01-02 |
WO2015041074A1 (ja) | 2015-03-26 |
JPWO2015041074A1 (ja) | 2017-03-02 |
JP6364417B2 (ja) | 2018-07-25 |
EP3048734A4 (en) | 2017-05-10 |
EP3048734A1 (en) | 2016-07-27 |
US10277257B2 (en) | 2019-04-30 |
KR20180133948A (ko) | 2018-12-17 |
KR20170077269A (ko) | 2017-07-05 |
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