MX2012013018A - Aparato y metodo para decodificacion por capas en un sistema de comunicacion utilizando codigos de verificacion de paridad de baja densidad. - Google Patents

Aparato y metodo para decodificacion por capas en un sistema de comunicacion utilizando codigos de verificacion de paridad de baja densidad.

Info

Publication number
MX2012013018A
MX2012013018A MX2012013018A MX2012013018A MX2012013018A MX 2012013018 A MX2012013018 A MX 2012013018A MX 2012013018 A MX2012013018 A MX 2012013018A MX 2012013018 A MX2012013018 A MX 2012013018A MX 2012013018 A MX2012013018 A MX 2012013018A
Authority
MX
Mexico
Prior art keywords
communication system
low
density
partiy
check codes
Prior art date
Application number
MX2012013018A
Other languages
English (en)
Inventor
Hyun-Koo Yang
Hong-Sil Jeong
Seho Myung
Jae-Yoel Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of MX2012013018A publication Critical patent/MX2012013018A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Abstract

Se proporciona un aparato y método de decodificación de canales en un sistema de comunicación que utiliza códigos de Verificación de Paridad de Baja Densidad (LDPC, por sus siglas en inglés) en el cual se recibe una señal codificada desde un transmisor y se decodifica utilizando una matriz de verificación de paridad. Se determina por lo menos uno de los órdenes de entrada y de los órdenes de salida de la matriz de verificación de paridad de tal manera que los mismos valores no se traslapan en una dirección de columna entre el por lo menos uno de los órdenes de entrada y de los órdenes de salida.
MX2012013018A 2010-05-11 2011-05-09 Aparato y metodo para decodificacion por capas en un sistema de comunicacion utilizando codigos de verificacion de paridad de baja densidad. MX2012013018A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100044165A KR20110124659A (ko) 2010-05-11 2010-05-11 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서 계층적 복호 장치 및 방법
PCT/KR2011/003444 WO2011142570A2 (en) 2010-05-11 2011-05-09 Apparatus and method for layered decoding in a communication system using low-density partiy-check codes

Publications (1)

Publication Number Publication Date
MX2012013018A true MX2012013018A (es) 2013-01-22

Family

ID=44912798

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2012013018A MX2012013018A (es) 2010-05-11 2011-05-09 Aparato y metodo para decodificacion por capas en un sistema de comunicacion utilizando codigos de verificacion de paridad de baja densidad.

Country Status (6)

Country Link
US (1) US8713397B2 (es)
EP (1) EP2569866A4 (es)
KR (1) KR20110124659A (es)
CA (1) CA2798963C (es)
MX (1) MX2012013018A (es)
WO (1) WO2011142570A2 (es)

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US9281841B2 (en) * 2012-10-31 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Load balanced decoding of low-density parity-check codes
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CN103731161B (zh) * 2014-01-09 2017-01-25 北京航空航天大学 一种用于ldpc码的交叠译码方法
US9413390B1 (en) * 2014-07-16 2016-08-09 Xilinx, Inc. High throughput low-density parity-check (LDPC) decoder via rescheduling
US20160020787A1 (en) * 2014-07-18 2016-01-21 Kabushiki Kaisha Toshiba Decoding apparatus, decoding method and non-transitory computer-readable recording medium containing a decoding program
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CA2864647C (en) 2014-08-14 2017-04-25 Sung-Ik Park Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same
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CA2864650C (en) 2014-08-14 2017-05-30 Sung-Ik Park Low density parity check encoder having length of 64800 and code rate of 2/15, and low density parity check encoding method using the same
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WO2022080975A1 (ko) * 2020-10-15 2022-04-21 삼성전자 주식회사 통신 또는 방송 시스템에서 데이터 복호화 방법 및 장치

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Also Published As

Publication number Publication date
US8713397B2 (en) 2014-04-29
EP2569866A2 (en) 2013-03-20
EP2569866A4 (en) 2013-10-09
CA2798963A1 (en) 2011-11-17
KR20110124659A (ko) 2011-11-17
CA2798963C (en) 2016-01-05
US20110283158A1 (en) 2011-11-17
WO2011142570A2 (en) 2011-11-17
WO2011142570A3 (en) 2012-04-19

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