MX2007010386A - Supresion de la actualizacion de un registro del historial en ramas por medio de ramas que terminan en bucle. - Google Patents

Supresion de la actualizacion de un registro del historial en ramas por medio de ramas que terminan en bucle.

Info

Publication number
MX2007010386A
MX2007010386A MX2007010386A MX2007010386A MX2007010386A MX 2007010386 A MX2007010386 A MX 2007010386A MX 2007010386 A MX2007010386 A MX 2007010386A MX 2007010386 A MX2007010386 A MX 2007010386A MX 2007010386 A MX2007010386 A MX 2007010386A
Authority
MX
Mexico
Prior art keywords
branch
loop
bhr
ending
detected
Prior art date
Application number
MX2007010386A
Other languages
English (en)
Inventor
Bohuslav Rychlik
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2007010386A publication Critical patent/MX2007010386A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Molds, Cores, And Manufacturing Methods Thereof (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)

Abstract

Se detectan instrucciones en ramas condicionales que terminan en bucles de codigo, y se impide que el registro historial en ramas (BHR) se actualice para almacenar evaluaciones en ramas que terminan en bucle. Esto evita que la rama que implementa iteraciones de bucle desplace otros historiales de evaluacion en ramas desde BHR. La rama que termina en bucle puede ser detectada estaticamente, por un compilador que utiliza una instruccion en ramas de tipo especifico o insertando bits indicadores en el codigo op de una instruccion en ramas que termina en bucle. Una instruccion en ramas que termina en bucle puede ser detectada dinamicamente como cualquier rama hacia atras, o almacenado el PC de la ultima o ultimas instrucciones una vez que se actualiza el BHR, y cotejando el PC de una instruccion en ramas con el(los) ultimo(s) registro(s) en ramas de PC (LBPC). Si el PC en ramas coincide, se suprime la actualizacion del BHR. La eliminacion de las ramas de iteracion de bucle fuera del BHR mejora el tiempo y precision del entrenamiento de prediccion en ramas.
MX2007010386A 2005-02-24 2006-02-24 Supresion de la actualizacion de un registro del historial en ramas por medio de ramas que terminan en bucle. MX2007010386A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/066,508 US20060190710A1 (en) 2005-02-24 2005-02-24 Suppressing update of a branch history register by loop-ending branches
PCT/US2006/006531 WO2006091778A2 (en) 2005-02-24 2006-02-24 Suppressing update of a branch history register by loop-ending branches

Publications (1)

Publication Number Publication Date
MX2007010386A true MX2007010386A (es) 2007-10-18

Family

ID=36577533

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2007010386A MX2007010386A (es) 2005-02-24 2006-02-24 Supresion de la actualizacion de un registro del historial en ramas por medio de ramas que terminan en bucle.

Country Status (11)

Country Link
US (1) US20060190710A1 (es)
EP (2) EP2270651A1 (es)
JP (3) JP5198879B2 (es)
KR (1) KR100930199B1 (es)
CN (2) CN103488463B (es)
AT (1) ATE483198T1 (es)
DE (1) DE602006017174D1 (es)
ES (1) ES2351163T3 (es)
IL (1) IL185362A0 (es)
MX (1) MX2007010386A (es)
WO (1) WO2006091778A2 (es)

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US10503538B2 (en) * 2014-06-02 2019-12-10 International Business Machines Corporation Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed
US10261826B2 (en) 2014-06-02 2019-04-16 International Business Machines Corporation Suppressing branch prediction updates upon repeated execution of an aborted transaction until forward progress is made
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US10635446B2 (en) * 2015-09-24 2020-04-28 Qualcomm Incorporated Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction
US9639370B1 (en) * 2015-12-15 2017-05-02 International Business Machines Corporation Software instructed dynamic branch history pattern adjustment
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US20180349144A1 (en) * 2017-06-06 2018-12-06 Intel Corporation Method and apparatus for branch prediction utilizing primary and secondary branch predictors
US10613867B1 (en) 2017-07-19 2020-04-07 Apple Inc. Suppressing pipeline redirection indications
CN111177663B (zh) * 2019-12-20 2023-03-14 青岛海尔科技有限公司 编译器的代码混淆改进方法及装置、存储介质、电子装置
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Also Published As

Publication number Publication date
IL185362A0 (en) 2008-02-09
ATE483198T1 (de) 2010-10-15
US20060190710A1 (en) 2006-08-24
EP1851620A2 (en) 2007-11-07
CN101160561B (zh) 2013-10-16
WO2006091778A3 (en) 2007-07-05
CN103488463A (zh) 2014-01-01
EP1851620B1 (en) 2010-09-29
JP5198879B2 (ja) 2013-05-15
KR100930199B1 (ko) 2009-12-07
JP2011100466A (ja) 2011-05-19
CN103488463B (zh) 2016-11-09
DE602006017174D1 (de) 2010-11-11
JP2008532142A (ja) 2008-08-14
WO2006091778A2 (en) 2006-08-31
ES2351163T3 (es) 2011-02-01
EP2270651A1 (en) 2011-01-05
JP2015007995A (ja) 2015-01-15
CN101160561A (zh) 2008-04-09
KR20070105365A (ko) 2007-10-30

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