DE602005017909D1 - Selektives durchführen von abrufvorgängen für speicheroperationen während der spekulativen ausführung - Google Patents

Selektives durchführen von abrufvorgängen für speicheroperationen während der spekulativen ausführung

Info

Publication number
DE602005017909D1
DE602005017909D1 DE602005017909T DE602005017909T DE602005017909D1 DE 602005017909 D1 DE602005017909 D1 DE 602005017909D1 DE 602005017909 T DE602005017909 T DE 602005017909T DE 602005017909 T DE602005017909 T DE 602005017909T DE 602005017909 D1 DE602005017909 D1 DE 602005017909D1
Authority
DE
Germany
Prior art keywords
processor
store
cache line
execution
speculative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005017909T
Other languages
English (en)
Inventor
Shailender Chaudhry
Marc Tremblay
Paul Caprioli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE602005017909D1 publication Critical patent/DE602005017909D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Electrophonic Musical Instruments (AREA)
DE602005017909T 2004-06-22 2005-05-11 Selektives durchführen von abrufvorgängen für speicheroperationen während der spekulativen ausführung Active DE602005017909D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US58239604P 2004-06-22 2004-06-22
US11/083,264 US7277989B2 (en) 2004-06-22 2005-03-16 Selectively performing fetches for store operations during speculative execution
PCT/US2005/016434 WO2006007075A2 (en) 2004-06-22 2005-05-11 Selectively performing fetches for store operations during speculative execution

Publications (1)

Publication Number Publication Date
DE602005017909D1 true DE602005017909D1 (de) 2010-01-07

Family

ID=34969468

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005017909T Active DE602005017909D1 (de) 2004-06-22 2005-05-11 Selektives durchführen von abrufvorgängen für speicheroperationen während der spekulativen ausführung

Country Status (5)

Country Link
US (1) US7277989B2 (de)
EP (1) EP1782184B1 (de)
AT (1) ATE450001T1 (de)
DE (1) DE602005017909D1 (de)
WO (1) WO2006007075A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008155806A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited バリア同期方法、装置、及びマルチコアプロセッサ
WO2013095508A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Speculative cache modification
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
US10949210B2 (en) 2018-05-02 2021-03-16 Micron Technology, Inc. Shadow cache for securing conditional speculative instruction execution
US11048636B2 (en) 2019-07-31 2021-06-29 Micron Technology, Inc. Cache with set associativity having data defined cache sets
US10915326B1 (en) 2019-07-31 2021-02-09 Micron Technology, Inc. Cache systems and circuits for syncing caches or cache sets
US11194582B2 (en) 2019-07-31 2021-12-07 Micron Technology, Inc. Cache systems for main and speculative threads of processors
US11200166B2 (en) 2019-07-31 2021-12-14 Micron Technology, Inc. Data defined caches for speculative and normal executions
US10908915B1 (en) 2019-07-31 2021-02-02 Micron Technology, Inc. Extended tags for speculative and normal executions
US11010288B2 (en) 2019-07-31 2021-05-18 Micron Technology, Inc. Spare cache set to accelerate speculative execution, wherein the spare cache set, allocated when transitioning from non-speculative execution to speculative execution, is reserved during previous transitioning from the non-speculative execution to the speculative execution
US11573802B2 (en) 2019-10-23 2023-02-07 Texas Instruments Incorporated User mode event handling

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065103A (en) * 1997-12-16 2000-05-16 Advanced Micro Devices, Inc. Speculative store buffer
US6665776B2 (en) 2001-01-04 2003-12-16 Hewlett-Packard Development Company L.P. Apparatus and method for speculative prefetching after data cache misses
WO2003001383A2 (en) 2001-06-26 2003-01-03 Sun Microsystems, Inc. Using an l2 directory to facilitate speculative loads in a multiprocessor system
US6925524B2 (en) * 2003-03-20 2005-08-02 Integrated Silicon Solution, Inc. Associated content storage system

Also Published As

Publication number Publication date
US7277989B2 (en) 2007-10-02
EP1782184B1 (de) 2009-11-25
WO2006007075A3 (en) 2006-09-21
EP1782184A2 (de) 2007-05-09
WO2006007075A2 (en) 2006-01-19
US20060020757A1 (en) 2006-01-26
ATE450001T1 (de) 2009-12-15

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