MX154702A - Mejoras a un subsistema de control para la transferencia de datos - Google Patents

Mejoras a un subsistema de control para la transferencia de datos

Info

Publication number
MX154702A
MX154702A MX196710A MX19671083A MX154702A MX 154702 A MX154702 A MX 154702A MX 196710 A MX196710 A MX 196710A MX 19671083 A MX19671083 A MX 19671083A MX 154702 A MX154702 A MX 154702A
Authority
MX
Mexico
Prior art keywords
data transfer
control subsystem
subsystem
control
transfer
Prior art date
Application number
MX196710A
Other languages
English (en)
Inventor
Edwin Jose Pnheiro
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX154702A publication Critical patent/MX154702A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
MX196710A 1982-04-30 1983-03-25 Mejoras a un subsistema de control para la transferencia de datos MX154702A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/373,366 US4517641A (en) 1982-04-30 1982-04-30 Lookahead I/O device control subsystem

Publications (1)

Publication Number Publication Date
MX154702A true MX154702A (es) 1987-12-01

Family

ID=23472116

Family Applications (1)

Application Number Title Priority Date Filing Date
MX196710A MX154702A (es) 1982-04-30 1983-03-25 Mejoras a un subsistema de control para la transferencia de datos

Country Status (5)

Country Link
US (1) US4517641A (es)
EP (1) EP0093239B1 (es)
JP (1) JPS58192124A (es)
DE (1) DE3380996D1 (es)
MX (1) MX154702A (es)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614312B2 (ja) * 1985-09-09 1994-02-23 株式会社日立製作所 回転型記憶装置の制御方法
JP2550063B2 (ja) * 1987-04-24 1996-10-30 株式会社日立製作所 分散処理システムのシミユレ−シヨン方式
JPS63310004A (ja) * 1987-06-12 1988-12-19 Omron Tateisi Electronics Co プログラマブル・コントロ−ラ
US5163132A (en) * 1987-09-24 1992-11-10 Ncr Corporation Integrated controller using alternately filled and emptied buffers for controlling bi-directional data transfer between a processor and a data storage device
JP2810043B2 (ja) * 1987-11-13 1998-10-15 株式会社日立製作所 データ処理装置
JPH01194006A (ja) * 1988-01-29 1989-08-04 Fanuc Ltd フロッピィディスク駆動用モータの制御装置
JPH02131732U (es) * 1989-04-01 1990-11-01
JPH02140527U (es) * 1989-04-28 1990-11-26
US5335328A (en) * 1989-06-28 1994-08-02 International Business Machines Corporation Methods for recording and reading data from a record member having data in any one of a plurality of block formats including determining length of records being transferred
CA2023998A1 (en) * 1989-11-13 1991-05-14 Thomas F. Lewis Apparatus and method for guaranteeing strobe separation timing
JP2818016B2 (ja) * 1990-08-09 1998-10-30 株式会社日立製作所 プロセス並列実行方法および装置
DE4029598A1 (de) * 1990-09-19 1992-03-26 Philips Patentverwaltung Schaltungsanordnung zur zeitweisen verzoegerung des programmablaufs in einem mikroprozessor
JPH087715B2 (ja) * 1990-11-15 1996-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理装置及びアクセス制御方法
US5237662A (en) * 1991-06-27 1993-08-17 Digital Equipment Corporation System and method with a procedure oriented input/output mechanism
JP3201786B2 (ja) * 1991-07-18 2001-08-27 アジレント・テクノロジー株式会社 ディジタル信号処理システムの制御方法
AU2418492A (en) * 1991-08-07 1993-03-02 Adaptec, Inc. Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive
JP3310402B2 (ja) * 1993-06-24 2002-08-05 株式会社三協精機製作所 マルチタスク制御コントローラ
US5598535A (en) * 1994-08-01 1997-01-28 International Business Machines Corporation System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions
US5590336A (en) * 1994-10-25 1996-12-31 Microsoft Corporation Method and apparatus for performing overlapping service of multiple IDE peripheral devices
US5838991A (en) * 1994-12-29 1998-11-17 International Business Machines Corporation Preemptable idle time activities for constant data delivery by determining whether initiating a host command will conflict with an idle time activity being executed
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5859853A (en) * 1996-06-21 1999-01-12 International Business Machines Corporation Adaptive packet training
US6553476B1 (en) * 1997-02-10 2003-04-22 Matsushita Electric Industrial Co., Ltd. Storage management based on predicted I/O execution times
US6092149A (en) * 1997-05-28 2000-07-18 Western Digital Corporation Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses
US5933611A (en) * 1997-06-23 1999-08-03 Opti Inc. Dynamic scheduler for time multiplexed serial bus
JPH11121582A (ja) * 1997-10-15 1999-04-30 Mitsubishi Electric Corp 半導体ウェハ製造設備制御方法および半導体ウェハ製造設備
US6298070B1 (en) 1998-05-07 2001-10-02 International Business Machines Corporation Packet training with an adjustable optimum number of packets
JP2000076027A (ja) * 1998-08-24 2000-03-14 Internatl Business Mach Corp <Ibm> 所定動作の実行方法、データ送信方法、プリンタ、下位システム、上位システム、所定動作の実行を管理する制御プログラムを格納した記録媒体、及び、データ送信を制御する制御プログラムを格納した記録媒体
US6915376B1 (en) * 1998-12-22 2005-07-05 Intel Corporation Host controlled optimization of disk storage devices
JP4237865B2 (ja) * 1999-04-27 2009-03-11 富士通マイクロエレクトロニクス株式会社 パケット転送制御装置及びその方法
US7603673B2 (en) * 2004-10-28 2009-10-13 Intel Corporation Method and system for reducing context switch times

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756420A (fr) * 1969-11-10 1971-03-01 Ibm Dispositif de transfert d'enregistrements
US4126895A (en) * 1975-12-29 1978-11-21 International Standard Electric Corporation Data processing system with monitoring and regulation of processor free time
US4200928A (en) * 1978-01-23 1980-04-29 Sperry Rand Corporation Method and apparatus for weighting the priority of access to variable length data blocks in a multiple-disk drive data storage system having an auxiliary processing device
US4262331A (en) * 1978-10-30 1981-04-14 Ibm Corporation Self-adaptive computer load control
US4392196A (en) * 1980-08-11 1983-07-05 Harris Corporation Multi-processor time alignment control system

Also Published As

Publication number Publication date
EP0093239A3 (en) 1986-02-05
DE3380996D1 (de) 1990-01-25
JPS58192124A (ja) 1983-11-09
US4517641A (en) 1985-05-14
JPH0248929B2 (es) 1990-10-26
EP0093239A2 (en) 1983-11-09
EP0093239B1 (en) 1989-12-20

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