KR980012239A - Device isolation structure of semiconductor device and method of manufacturing the same - Google Patents
Device isolation structure of semiconductor device and method of manufacturing the same Download PDFInfo
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- KR980012239A KR980012239A KR1019960027896A KR19960027896A KR980012239A KR 980012239 A KR980012239 A KR 980012239A KR 1019960027896 A KR1019960027896 A KR 1019960027896A KR 19960027896 A KR19960027896 A KR 19960027896A KR 980012239 A KR980012239 A KR 980012239A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
본 발명은 반도체장치의 평탄화에 유리할 뿐만 아니라 소자격리능력이 뛰어난 반도체장치의 소자격리구조 및 그 소자격리구조의 제조방법에 관한 것으로, 소자격리구조는 소자격리영역이 오목하게 형성된 기판에 형성된 반전방지층과, 그 반전방지층 위에 형성된 절연막과, 그 절연막 위에 형성된 것으로 소정의 전압을 인가받는 격리게이트를 포함하여 구성되고, 그 소자격리구조의 제조방법은 소자격리영역에 반전방지층과 필드산화막을 형성한 후, 그 필드산화막을 식각하는 단계와; 필드산화막이 식각됨으로써 오목하게 된 소자격리영역의 반전방지층 위에 절연층과 도전층을 차례대로 형성하는 단계와; 상기 도전층에 격리전압을 인가하기 위한 금속전극을 형성하는 단계로 구성된다. 이와 같은 소자격리구조는 반전방지층에 주입되는 도판트의 양과 격리게이트에 인가되는 전압의 극성 및 크기에 따라서 격리능력을 향상시킬 수 있는 장점이 있다.The present invention relates to a device isolation structure of a semiconductor device which is advantageous for planarization of a semiconductor device and which has an excellent device isolation capability, and a method of manufacturing the device isolation structure. The device isolation structure includes an anti- An insulating film formed on the anti-reflection layer, and a isolation gate formed on the insulating film and applied with a predetermined voltage. In the method for manufacturing the isolation structure, an anti-reflection layer and a field oxide film are formed in a device isolation region Etching the field oxide film; Forming an insulating layer and a conductive layer in this order on the anti-reflection layer of the element isolation region recessed by etching the field oxide film; And forming a metal electrode for applying an isolation voltage to the conductive layer. Such an element isolation structure has an advantage that the isolation ability can be improved according to the amount of the dopant injected into the anti-reverse layer and the polarity and magnitude of the voltage applied to the isolation gate.
Description
제1도는 종래의 소자격리구조를 포함한 반도체장치의 부분단면도.FIG. 1 is a partial cross-sectional view of a semiconductor device including a conventional isolation structure. FIG.
제2도는 종래의 소자격리구조를 포함한 DRAM의 대략적인 구성단면도.FIG. 2 is a schematic structural cross-sectional view of a DRAM including a conventional isolation structure; FIG.
제3도는 본 발명에 따른 소자격리구조 제조방법을 도시한 공정수순도.FIG. 3 is a process flow chart showing a method of manufacturing a device isolation structure according to the present invention; FIG.
제4도는 상기 제3도에 도시된 공정수순도를 통해 형성된 반도체장치의 개략적인 평면도.FIG. 4 is a schematic plan view of a semiconductor device formed through the process flow diagram shown in FIG. 3; FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
101 : 기판 102 : 필드산화막101: substrate 102: field oxide film
103 : 반전방지층 104 : 질화막103: anti-reverse prevention layer 104: nitride film
105 : 다결정실리콘층 106 : 게이트산화막105: polycrystalline silicon layer 106: gate oxide film
107 : 게이트 108 : 소오스/드레인영역107: gate 108: source / drain region
121 : 소자형성영역 122 : 소자격리영역121: element formation region 122: element isolation region
123 : 콘택123:
본 발명은 반도체장치에 관한 것으로, 특히 반도체장치의 평탄화(스텝커버리지)에 유리할 뿐만 아니라 소자격리능력이 뛰어난 반도체장치의 소자격리구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device isolation structure of a semiconductor device which is advantageous not only in planarization (step coverage) of a semiconductor device but also in device isolation capability, and a manufacturing method thereof.
디램(DRAM)과 같은 반도체장치의 각각의 소자는 다른 소자와 다른 소자와 전기적으로 분리될 필요성이 있다. 이에 따라 다양한 소자격리구조가 제안되고 있는데, 그러한 소자격리구조는 인접된 소자간에 바람직하지 못한 관계가 발생하지 않도록 하는 함과 동시에 반도체장치의 집적도를 향상시키는 중요한 요소가 되므로, 소자격리영역이 작으면서도 소자격리능력이 뛰어나도록 하여야 한다.Each element of a semiconductor device, such as DRAM (DRAM), needs to be electrically isolated from other elements and other elements. As a result, various element isolation structures have been proposed. Such element isolation structures are important elements for improving the integration degree of semiconductor devices while preventing an undesirable relation between adjacent elements, and therefore, The device isolation capability shall be excellent.
제1도는 종래 기술에 따른 소자격리구조의 일례를 설명하기 위한 반도체장치의 부분단면도로서, 소자격리영역의 기판(11)에 BF2 -을 주입하여 형성한 반전방지층(13)과, 그 기판(11)에 대한 산화공정으로 상기 반전방지층(13) 위에 형성되는 필드산화막(12)으로 소자격리구조를 형성한 후, 게이트산화막(14)과 게이트(15) 및 소오스/드레인영역(16)을 차례대로 형성하는 공정을 나타내고 있다. 그리고 제 2 도는 상기 제 1 도에 도시된 소자격리구조를 포함하여 구성된 디램(DRAM)의 구성단면도로서, 반전방지층(13)과 필드산화막(12)으로 구성된 소자격리구조와, 소자형성영역 및 소자격리영역의 필드산화막(12) 위에 형성된 게이트산화막(14) 및 게이트(15)와, 소자형성영역의 기판(11)에 이온이 주입되어 형성된 LDD구조의 소오스/드레인영역(16)과, 하부전극(SG)(17)과 유전막(18) 및 상부전극(TG)(19)으로 구성된 캐패시터를 보여주고 있다.FIG. 1 is a partial cross-sectional view of a semiconductor device for explaining an example of a device isolation structure according to the related art, which includes an anti-reflection layer 13 formed by implanting BF 2 - into a substrate 11 of a device isolation region, The gate oxide film 14, the gate 15 and the source / drain region 16 are sequentially formed after the element isolation structure is formed by the field oxide film 12 formed on the anti-reflection layer 13 by the oxidation process for the gate oxide film 14, As shown in FIG. And FIG. 2 is a structural cross-sectional view of a DRAM (DRAM) including the element isolation structure shown in FIG. 1, including a device isolation structure composed of an inversion preventing layer 13 and a field oxide film 12, A gate oxide film 14 and a gate 15 formed on the field oxide film 12 of the isolation region and source and drain regions 16 of an LDD structure formed by implanting ions into the substrate 11 in the element formation region, (SG) 17, a dielectric film 18, and an upper electrode TG 19.
이와 같은 종래 소자격리구조의 제조방법은 소자형성영역의 기판(11) 위에 확산 및 산화를 방지하기 위한 마스크패턴을 형성한 후, 확산공정과 산화공정을 차례대로 수행하여 반전방지층(13)과 필드산화막(12)을 형성하는 단계로 이루어졌다.In this conventional method for fabricating a device isolation structure, a mask pattern for preventing diffusion and oxidation is formed on a substrate 11 in an element formation region, and then a diffusion process and an oxidation process are sequentially performed to form an anti- To form an oxide film (12).
그러나 상기 종래 소자격리구조는, 산화공정을 통해 형성되는 필드산화막이 기판 아래쪽보다 기판 위쪽에서 빠르게 형성(기판 위쪽과 아래쪽의 성장속도비가 약 6 : 4)되기 때문에, 반도체장치의 평탄도(스텝커버리지)가 나빠지는 단점이 있었다. 이는 필드산화막 위에 게이트가 형성된 모습을 보여주고 있는 제 2 도의 단면도를 통해 알 수 있는 바와 같다. 그 뿐만 아니라, 소자의 미세화와 함께 그 소자를 격리하기 위한 소자격리영역의 크기가 감소하게 되면, 그 소자격리영역에 형성되는 상기 반전방지층과 필드산화막의 소자격리능력이 떨어지게 되어, 소자의 미세화와 함께 소자격리영역을 감소시키지 못하게 되므로 반도체장치의 고집적도에 불리한 단점이 있다.However, in the conventional device isolation structure, since the field oxide film formed through the oxidation process is formed at a higher rate than the substrate below the substrate (the growth rate ratio of the upper and lower sides of the substrate is about 6: 4), the flatness ) Is deteriorated. This can be seen from the cross-sectional view of FIG. 2 which shows the gate formed on the field oxide film. In addition, when the device is miniaturized and the size of the device isolation region for isolating the device is reduced, the device isolation capability of the inversion prevention layer and the field oxide film formed in the device isolation region is deteriorated, The device isolation region can not be reduced together, which is disadvantageous to the high degree of integration of the semiconductor device.
이에 본 발명은 상기 종래 기술의 문제점을 해결하기 위한 것으로, 반도체장치의 평탄화에 유리할 뿐만 아니라 소자격리능력이 뛰어난 반도체장치의 소자격리구조 및 그 소자격리구조의 제조방법을 제공함에 그 목적을 둔다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a device isolation structure for a semiconductor device which is advantageous for planarization of a semiconductor device and which has an excellent device isolation capability, and a method for manufacturing the device isolation structure.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 소자격리구조는 소자격리영역이 오목하게 형성된 기판에 형성된 반전방지층과, 그 반전방지층 위에 형성된 절연막과, 그 절연막 위에 형성된 것으로 소정의 전압을 인가받는 격리게이트를 포함하여 구성되는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a device isolation structure for a semiconductor device, the device isolation structure including: an anti-reflection layer formed on a substrate on which a device isolation region is recessed; an insulation film formed on the anti-reflection layer; And an isolation gate.
이와 같이 구성된 소자격리구조는 상기 반전방지층에 주입되는 도판트의 양을 조절함으로써 그 소자격리구조의 격리능력을 향상시킬 수 있을 뿐만 아니라 격리게이트에 인가되는 전압의 극성 및 크기에 따라서도 격리능력을 향상시킬 수 있다. 이에 따라 소자격리구조를 더 작게 형성할 수 있게 됨으로써, 반도체장치의 집적도에도 유리한 장점이 있다.The device isolation structure thus configured not only improves the isolation capability of the device isolation structure by adjusting the amount of the dopant injected into the inversion prevention layer but also improves the isolation ability depending on the polarity and size of the voltage applied to the isolation gate. Can be improved. As a result, the device isolation structure can be formed to be smaller, which is advantageous also for the degree of integration of the semiconductor device.
그리고 상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 소자격리구조 제조방법은 소자격리영역에 반전방지층과 필드산화막을 형성한 후, 그 필드산화막을 식각하는 단계와; 필드산화막이 식각됨으로써 오목하게된 소자격리영역의 반전방지층 위에 절연층과 도전층을 차례대로 형성하는 단계와; 상기 도전층에 격리전압을 인가하기 위한 금속전극을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method for fabricating a device isolation structure for a semiconductor device, comprising: forming an anti-reflection layer and a field oxide layer on a device isolation region; Forming an insulating layer and a conductive layer in this order on the anti-reflection layer of the element isolation region recessed by etching the field oxide film; And forming a metal electrode for applying an isolation voltage to the conductive layer.
이하 첨부된 제 3 도의 공정수순도를 참조하여, 본 발명에 따른 소자격리구조를 포함하여 구성되는 DRAM제조방법의 일부에 대해서 상세히 설명한다.A part of a method of manufacturing a DRAM including the element isolation structure according to the present invention will be described in detail with reference to the process flow chart of FIG.
제3(가)도에 도시된 바와 같이, 소자격리영역에 BF2 -를 주입한 반전방지층(103)과 기판(101)이 산화되어 형성된 필드산화막(102)을 종래와 같은 기술로 형성한 후, 제2(가)도에 도시된 바와 같이 상기 필드산화막(102)을 실리콘에 대한 식각선택성이 우수한 습식각법으로 식각한 후, 그 결과물의 전면에 질화막(또는 산화막; 이하 같다)(104)을 증착한 다음, 그를 패터닝하여 필드산화막(102)이 식각된 상기 소자격리영역에 질화막(104)을 형성하고, 이어서 그 질화막(104)을 포함하는 소자의 전면에 다결정실리콘을 증착한 후, 그를 패터닝하여 상기 질화막(104) 위에 다결정실리콘층(105)을 형성한다. 이와 같이 필드산화막의 제거로 오목하게 된 소자격리영역에 질화막(104)과 다결정실리콘층(105)이 형성됨으로써, 그 영역이 평탄하게 된다.As shown in FIG. 3 (a), after forming the anti-reflection layer 103 in which BF 2 - is implanted in the element isolation region and the field oxide film 102 formed by oxidizing the substrate 101 by a conventional technique , The field oxide film 102 is etched by a wet etching method having excellent etching selectivity for silicon, and a nitride film (or an oxide film) 104 is formed on the entire surface of the resultant structure A nitride film 104 is formed on the device isolation region where the field oxide film 102 is etched and then polysilicon is deposited on the entire surface of the device including the nitride film 104. Then, And a polycrystalline silicon layer 105 is formed on the nitride film 104. As described above, the nitride film 104 and the polycrystalline silicon layer 105 are formed in the element isolating region recessed by the removal of the field oxide film, so that the region becomes flat.
이어서 제2(다)도에 도시된 바와 같이 상기 소자형성영역과 소자분리영역에 게이트산화막(106)과 게이트(107) 및 N형 소오스/드레인영역(108)을 순차적으로 형성한 후, 그 결과물 위에 층간절연막(미도시)을 증착하고, 이어서 상기 다결정실리콘층(105)과 접촉하는 금속전극을 형성한다.Next, a gate oxide film 106, a gate 107 and an n-type source / drain region 108 are sequentially formed in the element formation region and the element isolation region as shown in FIG. 2 (c) An interlayer insulating film (not shown) is deposited on the polysilicon layer 105, and then a metal electrode which is in contact with the polysilicon layer 105 is formed.
그리고 제4도는 상기 제3도의 제조방법을 통해 형성된 DRAM의 대략적인 평면도로서, 이에 도시된 바와 같이 반전방지층(103)과 질화막(104) 및 다결정실리콘층(105)이 차례대로 형성된 소자분리영역(122)이 각 소자형성영역(121)을 완전히 포위함으로써, 그 각 소자가 다른 소자와 완전히 격리되었음을 보여주고 있다. 그리고 층간절연막을 사이에 두고 있는 소자격리영역의 다결정실리콘층(105)과 금속전극을 연결하기 위한 콘택(124)은 넓은 소자격리영역에서 선택되는 소정의 다수 지점에 형성될 수 있음을 보여주고 있다.FIG. 4 is a schematic plan view of a DRAM formed through the manufacturing method of FIG. 3. As shown in FIG. 3, an anti-reflection layer 103, a nitride film 104 and a polycrystalline silicon layer 105 122 completely enclose each element formation region 121, thereby showing that each element thereof is completely isolated from the other elements. And the contact 124 for connecting the metal electrode to the polycrystalline silicon layer 105 of the element isolation region sandwiched between the interlayer insulating films can be formed at a predetermined plurality of points selected from a wide element isolation region .
이와 같이 과정을 통해 형성된 소자격리구조는, 금속전극에 음전압을 인가하면 그 음전압에 의하여 형성된 전계가 질화막(104) 아래의 반전방지층(103) BF2 -이온을 그 질화막(104)과 반전방지층(103)의 계면에 집중시킴으로써, 그 BF2 -이온이 형성하는 P형 도전영역과 각 소자의 N형 소오스/드레인영역(108)이 형성하는 접합을 강화시킨다. 이에 따라 각각의 소자는 완벽하게 전기적으로 격리된다.When a negative voltage is applied to the metal electrode, the electric field formed by the negative voltage causes the BF 2 - ions in the anti-reflection layer 103 under the nitride film 104 to react with the nitride film 104, Diffusion layer 103 to enhance the junction formed by the P-type conductive region formed by the BF 2 - ions and the N-type source / drain region 108 of each element. As a result, each device is completely electrically isolated.
이상에서 상술한 바와 같이 본 발명에 따른 소자격리구조는 필드산화막이 제거된 영역에 절연막과 도전층을 형성함으로써 그 표면을 평탄하게 할 뿐만 아니라 반전방지층에 주입되는 이온의 양과 격리게이트에 인가되는 전압의 크기를 조절함으로써 소자격리능력을 향상시키는 효과가 있다.As described above, the element isolating structure according to the present invention not only flatens the surface of the insulating layer and the conductive layer in the area where the field oxide layer is removed, but also increases the amount of ions implanted into the anti- Thereby improving the device isolation capability.
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KR100322142B1 (en) * | 1998-06-08 | 2002-02-06 | 가타오카 마사타카 | Structure for mounting flexible printed circuit board and recording and playbacking apparatus using the same |
US7859851B2 (en) | 2004-12-09 | 2010-12-28 | Samsung Electronics Co., Ltd. | Flexible printed circuit and bracket structure for hard disk drive |
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KR100322142B1 (en) * | 1998-06-08 | 2002-02-06 | 가타오카 마사타카 | Structure for mounting flexible printed circuit board and recording and playbacking apparatus using the same |
US7859851B2 (en) | 2004-12-09 | 2010-12-28 | Samsung Electronics Co., Ltd. | Flexible printed circuit and bracket structure for hard disk drive |
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