KR980007404A - Time slot switch between processor and device - Google Patents

Time slot switch between processor and device Download PDF

Info

Publication number
KR980007404A
KR980007404A KR1019960024059A KR19960024059A KR980007404A KR 980007404 A KR980007404 A KR 980007404A KR 1019960024059 A KR1019960024059 A KR 1019960024059A KR 19960024059 A KR19960024059 A KR 19960024059A KR 980007404 A KR980007404 A KR 980007404A
Authority
KR
South Korea
Prior art keywords
signal
unit
outputting
data
clock
Prior art date
Application number
KR1019960024059A
Other languages
Korean (ko)
Other versions
KR100208227B1 (en
Inventor
김재평
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019960024059A priority Critical patent/KR100208227B1/en
Priority to US08/882,537 priority patent/US5966383A/en
Publication of KR980007404A publication Critical patent/KR980007404A/en
Application granted granted Critical
Publication of KR100208227B1 publication Critical patent/KR100208227B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/52—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing

Abstract

본 발명은 프로세서(P1, P2)와 디바이스(D1-D16)들간의 이중화로 연결된 타임 슬롯 스위치로에 관한 것으로서, 프레임 동기 신호(FS) 및 클럭 신호(CLK)를 출력하는 클럭 및 동기 발생부(1)와; 액티브 신호(ACT)에 따라 구동하여 수신 데이터(RXD) 및 알람신호를 상기 프레임 동기 신호(FS) 및 클럭(CLK)에 동기되어 상기 프로세서(P1, P2)에 인가하며, 상기 프로세서(P1, P2)로부터 인가되는 데이터(TXD)를 수신하여 프레임 동기 신호(FS) 및 클럭(CLK)와 함께 출력하며, 소정의 선택 신호를 출력하는 인터페이스부(2)와; 상기 인터페이스부(2)의 데이터(TXD)를 프레임 동기 신호(FS) 및 클럭(CLK)에 동기되어 디바이스(D1-D16)에 분배하는 분배부(3)와; 디바이스(D1-D16)들로부터의 데이터(RXD)를 취합하여 상기 인터페이스부(2)에 인가하는 정합부(4)와; 디바이스(D1-D16)들로부터의 알람 신호 및 이중화용 상대 타임 슬롯 스위치에 인가되는 상기 알람 신호들을 상기 선택 신호에 따라 상기 인디페이스부(2)에 인가하는 알람 취함부(5)와; 클럭 및 동기 발생부(1)와 전원 공급 상태의 정상 여부를 체킹하여 작동 고정 신호 및 전원 고장 신호를 출력하는 상태 검사부(7)와; 작동 고장 신호 및 전원 고장 신호 및 이중화용 상태 타임 슬롯 스위치로부터 액티브 신호의 인가여부에 따라 상가 액티브 신호(ACT)를 선택적으로 출력하는 이중화 제어부(8)를 포함한다. 즉, 본 발명의 타임슬롯 스위치는 상술한 바와 같이 프로세서(P1, P2)로부터 인가되는 데이터(TXD)를 분배부(3)를 통하여 디바이스(D1-D16)에 선택적으로 분배하는 한편, 디바이스(D1-D16)들로부터 인가되는 데이터(RXD) 및 알람 신호들을 프로세서에 선택적으로 인가할 수 있다는 효과가 있다.The present invention relates to a time slot switch connected by redundancy between processors P1 and P2 and devices D1 to D16 and includes a clock and synchronous generator for outputting a frame synchronous signal FS and a clock signal CLK 1); And applies the received data RXD and an alarm signal to the processors P1 and P2 in synchronism with the frame synchronizing signal FS and the clock CLK in accordance with the active signal ACT, An interface unit 2 for receiving data (TXD) applied from a video decoder (not shown) and outputting the data together with a frame synchronizing signal (FS) and a clock (CLK), and outputting a predetermined selection signal; A distributing unit 3 for distributing the data TXD of the interface unit 2 to the devices D1 to D16 in synchronization with the frame synchronizing signal FS and the clock CLK; A matching unit 4 for collecting data RXD from the devices D1 to D16 and applying the data RXD to the interface unit 2; An alarm take-over unit 5 for applying an alarm signal from the devices D1 to D16 and the alarm signals applied to the relative time slot switch for redundancy to the indication unit 2 according to the selection signal; A state checking unit 7 for checking the clock and synchronous generating unit 1 and the normal state of the power supply state and outputting an operation fixing signal and a power supply failure signal; And a redundancy control unit 8 for selectively outputting an active signal ACT according to whether an operation failure signal, a power supply failure signal, and an active signal from a redundancy state time slot switch are applied. That is, the time slot switch of the present invention selectively distributes the data TXD applied from the processors P1 and P2 to the devices D1 to D16 via the distributor 3 as described above, The data RXD and the alarm signals applied from the data buses D16 to D16 can be selectively applied to the processor.

Description

프로세서와 디바이스간의 타임 슬롯 스위치Time slot switch between processor and device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 타임 슬롯 스위치가 프로세서 및 디바이스들 사이에 구성되는 상태를 도시한 블록도.FIG. 1 is a block diagram showing a state in which a timeslot switch according to the present invention is configured between a processor and devices. FIG.

제2도는 본 발명의 따른 프로세서와 디바이스간의 타임 슬롯 스위치의 블록도.Figure 2 is a block diagram of a timeslot switch between a processor and a device in accordance with the present invention;

제3도는 본 발명에 따른 프로세서오 디바이스간의 타임 슬롯 스위치에서 액티브/스탠 바이 상태의 설정 과정을 도시한 도면.FIG. 3 is a diagram illustrating a process of setting an active / standby state in a timeslot switch between processor defective devices according to the present invention; FIG.

Claims (1)

프로세서(P1, P2)와 디바이스(D1-D16)들간의 이중화로 연결된 타임 슬롯 스위치로서, 프레임 동기 신호(CLK)를 출력하는 클럭 및 동기 발생부(1)와; 액티브 신호(FS) 및 클릭신호(ACT)에 따라 구동하여 수신 데이터(RXD) 및 알람신호를 상기 프레임 동기 신호(FS) 및 클럭(CLK)에 동기되어 상기 프로세서(P1, P2)에 인가하며, 상기 프로세서(P1, P2)로부터 인가되는 데이터(TXD)를 수신하여 프레임 동기 신호(FS) 및 클럭(CLK)와 함께 출력하며, 소정의 선택 신호를 출력하는 인터페이스부(2)와; 사이 인터페이스부(2)의 데이터(TXD)를 프레임 동기 신호(FS) 및 클럭(CLK)에 동기되어 상기 디바이스(D1-D16)에 분배하는 분배부(3)와; 상기 디바이스(D1-D16)들로부터의 데이터(RXD)를 취합하여 상기 인터페이스부(2)에 인가하는 정합부(4)와; 상기 디바이스(D1-D16)들로부터의 알람 신호 및 이중화용 상대 타임 슬롯 스위치에 인가되는 상기 알랍 신호들을 상기 선택 신호에 따라 상기 인디페이스부(2)부에 인가하는 알람 취합부(5)와; 상기 클럭 및 동기 발생부(1)와 전원 공급 상태의 정상 여부를 체킹하여 작동 고장 신호 및 전원 고장 신호를 출력하는 상태 검사부(7)와; 상기 작동 고장 신호 및 전원 고장 신호 및 이중화용 상태 타임 슬롯 스위치로부터 액티브신호의 인가여부에 따라 상가 액티브 신호(ACT)를 선택적으로 출력하는 이중화 제어부(8)를 포함하는 프로세스 디바이스간의 타임 슬롯 스위치.A clock and synchronous generator (1) for outputting a frame synchronous signal (CLK) as a time slot switch connected in duplication between processors (P1, P2) and devices (D1-D16); Is driven in accordance with the active signal FS and the click signal ACT to apply the received data RXD and the alarm signal to the processors P1 and P2 in synchronization with the frame synchronizing signal FS and the clock CLK, An interface unit 2 for receiving data TXD applied from the processors P1 and P2 and outputting the data together with a frame synchronizing signal FS and a clock CLK and outputting a predetermined selection signal; A distribution unit 3 for distributing the data TXD of the interface unit 2 to the devices D1 to D16 in synchronization with the frame synchronizing signal FS and the clock CLK; A matching unit 4 for collecting data RXD from the devices D1 to D16 and applying the data RXD to the interface unit 2; An alarm collecting unit 5 for applying the alarm signal from the devices D1 to D16 and the alarm signals applied to the relative time slot switch for redundancy to the indications unit 2 according to the selection signal; A state checking unit 7 for checking whether the power supply state is normal with the clock and synchronization generating unit 1 and outputting an operation failure signal and a power supply failure signal; And a redundancy control unit (8) for selectively outputting an active signal (ACT) according to whether the operation failure signal, the power supply failure signal, and the redundancy state time slot switch are applied.
KR1019960024059A 1996-06-26 1996-06-26 Time slot switch between processor and device KR100208227B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019960024059A KR100208227B1 (en) 1996-06-26 1996-06-26 Time slot switch between processor and device
US08/882,537 US5966383A (en) 1996-06-26 1997-06-25 Data communication system using a time slot interface architecture between processor and devices therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024059A KR100208227B1 (en) 1996-06-26 1996-06-26 Time slot switch between processor and device

Publications (2)

Publication Number Publication Date
KR980007404A true KR980007404A (en) 1998-03-30
KR100208227B1 KR100208227B1 (en) 1999-07-15

Family

ID=19463584

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960024059A KR100208227B1 (en) 1996-06-26 1996-06-26 Time slot switch between processor and device

Country Status (1)

Country Link
KR (1) KR100208227B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000061025A (en) * 1999-03-23 2000-10-16 김영환 Device for holding data tester in common

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428660B1 (en) * 2000-10-30 2004-04-30 엘지전자 주식회사 A method of alternating handler for exchanger

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000061025A (en) * 1999-03-23 2000-10-16 김영환 Device for holding data tester in common

Also Published As

Publication number Publication date
KR100208227B1 (en) 1999-07-15

Similar Documents

Publication Publication Date Title
ATE190794T1 (en) SIGNAL PROCESSING SYSTEM
EP0817055A3 (en) Computer system host switching
CA2216525A1 (en) Clock control system and method
ES2121532A1 (en) Synchronized video/audio alarm system
TW353176B (en) A semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor
JPH0638644B2 (en) Character figure display circuit
KR980007404A (en) Time slot switch between processor and device
TW328603B (en) Method and apparatus for distributing clock signal to synchronous memory element
GB2319441A (en) Split bus architecture for multipoint control unit
KR20010046715A (en) Apparatus and method for bus interface for optical module
KR100328757B1 (en) A error preventing device of clock signal with switchover for transmission system
KR20000011955U (en) Clock Distribution Time Division Switch Unit to Prevent Clock Errors
JP2776417B2 (en) Multiplexed clock distribution method
KR930003828B1 (en) Credit card monitoring apparatus and monitoring method therefor
JP2797826B2 (en) Bus interface circuit
JPH01137494A (en) Memory device
KR200167747Y1 (en) Dc bus loop-back test system for exchange
JPH086664A (en) Computer and its clock switching method
JPH0398320A (en) Switching control system for active/standby package constituting redundant system
KR970066895A (en) SYSTEM SYNCHRONIZATION DEVICE AND METHOD FOR BUS SYSTEM
KR930008727B1 (en) Method of controlling a input clock selecting
JP2874444B2 (en) Line monitoring circuit
KR100487242B1 (en) Redundant Implement Device
KR0169370B1 (en) Signal process circuit of liquid crystal system for data enable signal priority process
JPS6251013B2 (en)

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020415

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee