KR980006506A - 모스트랜지스터 제조방법 - Google Patents

모스트랜지스터 제조방법 Download PDF

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Publication number
KR980006506A
KR980006506A KR1019960025383A KR19960025383A KR980006506A KR 980006506 A KR980006506 A KR 980006506A KR 1019960025383 A KR1019960025383 A KR 1019960025383A KR 19960025383 A KR19960025383 A KR 19960025383A KR 980006506 A KR980006506 A KR 980006506A
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South Korea
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forming
film
polysilicon film
titanium
impurity
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KR1019960025383A
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KR100204015B1 (ko
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황준
김천수
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김주용
현대전자산업주식회사
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Publication of KR100204015B1 publication Critical patent/KR100204015B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야 전계효과 트랜지스터
2. 발명이 해결하려고 하는 기술적인 과제 전계효과 트랜지스터 제조방법, 특히 균일한 면저항을 갖는 실리사이드(Salicide)를 형성함에 있어서, 고농도 n형 불순물이 도핑된 폴리실리콘 막상에서는 티타륨 셀리사이드막의 상변환이 용이하지 않아 소자의 신뢰성이 저하되는 문제점이 있었음.
3. 발명의 해결방법의 요지 티타륨 셀리사이드막의 상변환을 위해 실리콘 이온을 선행 도핑하여 티타륨 셀리사이드막(TiSi2)의 상변환을 용이하게 구현하는 방법을 제공하고자 함.
4. 발명의 중요한 용도 전계효과 트랜지스터이 균일한 면저항과 용이한 상변환을 갖는 셀리사이드를 형성하는데 이용됨.

Description

모스트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2c도는 본 발명에 따른 모스트랜지스터 제조공정도.

Claims (4)

  1. 반도체 장치의 제조방법에 있어서, 반도체 기판상에 게이트 절연막과 비도핑된 폴리실리콘막 패턴을 형성하는 단계; 상기 비도핑된 폴리실리콘막 패턴에 의해 노출된 상기 반도체 기판에 저농도 불순물 이온주입 영역을 형성하는 단계; 상기 비도핑된 폴리실리콘막 측벽에 절연막 스페이서를 형성하고 전체구조상부에 티타늄막을 형성하는 단계; 상기 티타늄막 상에 실리콘 이온을 도핑하고, 제1 급속열처리 (RTA) 하는 단계; 상기 비도핑된 폴리실리콘막 및 상기 저농도 불순물 이온주입 영역 상부를 제외한 지역의 상기 티타늄막을 선택식각하여 제거하는 단계; 제2 급속열처리(RTA)를 실시하여 상기 잔류 티타늄막을 실리사이드화 하는 단계; 및 고농도 불순물을 이온주입하여 상기 폴리실리콘막을 도핑시키고 소오스/드레인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 모스트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 비도핑된 게이트 전극에 불순물 이온주입한 것은 저농도 n형 불순물인 인(P)인 것을 특징으로 하는 모스트랜지스터 제조방법.
  3. 제1항에 있어서, 상기 소오스/드레인 영역의 불순물 이온주입한 것은 고농도 n형 불순물인 비소(As)인 것을 특징으로 하는 모스트랜지스터 제조방법.
  4. 제1항에 있어서, 2차 금속열처리 공정의 온도는 1000℃ 내지 1100℃인 것을 특징으로 하는 모스트랜지스터 제조방법.
KR1019960025383A 1996-06-28 1996-06-28 모스트랜지스터 제조방법 KR100204015B1 (ko)

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KR1019960025383A KR100204015B1 (ko) 1996-06-28 1996-06-28 모스트랜지스터 제조방법

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KR1019960025383A KR100204015B1 (ko) 1996-06-28 1996-06-28 모스트랜지스터 제조방법

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KR980006506A true KR980006506A (ko) 1998-03-30
KR100204015B1 KR100204015B1 (ko) 1999-06-15

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KR20030048548A (ko) * 2001-12-12 2003-06-25 주식회사 하이닉스반도체 반도체 장치의 제조 방법

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