KR980006481A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR980006481A
KR980006481A KR1019960023647A KR19960023647A KR980006481A KR 980006481 A KR980006481 A KR 980006481A KR 1019960023647 A KR1019960023647 A KR 1019960023647A KR 19960023647 A KR19960023647 A KR 19960023647A KR 980006481 A KR980006481 A KR 980006481A
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South Korea
Prior art keywords
melting point
forming
high melting
point metal
substrate
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KR1019960023647A
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Korean (ko)
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KR100390817B1 (en
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김천수
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김주용
현대전자산업주식회사
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Priority to KR1019960023647A priority Critical patent/KR100390817B1/en
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Publication of KR100390817B1 publication Critical patent/KR100390817B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 Ti실리사이드 형성시 불순물의 도입을 최대한 억제하여 그 특성을 향상시킬 수 있도록 한 것으로, 실리콘기판상에 게이트산화막을 형성하는 단계와, 상기 게이트산화막상부에 그 내부에 산소 성분이 존재하지 않는 폴리실리콘층을 형성하는 단계, 상기 폴리실리콘층을 소정패턴으로 패터닝하여 게이트전극을 형성하는 단계, 기판 전면에 로드록 시스템을 이용하여 질화막을 형성하는 단계, 이온주입을 실시하여 기판 소정영역에 소오스 및 드레인영역을 형성하는 단계, 상기 질화막을 제거하는 단계, 기판상에 고융점금속을 증착하는 단계, 및 열처리를 행하여 상기 고융점금속과 이 고융점금속과 접촉된 Si이 포함된 부분을 반응시켜 고융점금속 실리사이드를 형성하는 단계로 이루어지는 반도체소자의 제조방법을 제공한다.The present invention is to minimize the introduction of impurities in the formation of Ti silicide to improve the characteristics, to form a gate oxide film on a silicon substrate, there is no oxygen component therein on the gate oxide film Forming a polysilicon layer, patterning the polysilicon layer in a predetermined pattern, forming a gate electrode, forming a nitride film using a load lock system on the entire surface of the substrate, and implanting an ion into the source region And forming a drain region, removing the nitride film, depositing a high melting point metal on a substrate, and performing a heat treatment to react the high melting point metal with a portion containing Si in contact with the high melting point metal. It provides a method for manufacturing a semiconductor device comprising the step of forming a high melting point metal silicide.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도 내지 제1d도는 본 발명에 의한 반도체소자 제조방법을 도시한 공정순서도이다.1A to 1D are process flowcharts showing a method of manufacturing a semiconductor device according to the present invention.

Claims (6)

실리콘기판상에 게이트산화막을 형성하는 단계와, 상기 게이트산화막상부에 그 내부에 산소 성분이 존재하지 않는 폴리실리콘층을 형성하는 단계, 상기 폴리실리콘층을 소정패턴으로 패터닝하여 게이트전극을 형성하는 단계, 기판 전면에 로드록 시스템을 이용하여 질화막을 형성하는 단계, 이온주입을 실시하여 기판 소정영역에 소오스 및 드레인영역을 형성하는 단계, 상기 질화막을 제거하는 단계, 기판상에 고융점금속을 증착하는 단계, 및 열처리를 행하여 상기 고융점금속과 이 고융점금속과 접촉된 Si이 포함된 부분을 반응시켜 고융점금속 실리사이드를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.Forming a gate oxide film on a silicon substrate, forming a polysilicon layer having no oxygen component thereon on the gate oxide film, and patterning the polysilicon layer in a predetermined pattern to form a gate electrode Forming a nitride film using a load lock system on the entire surface of the substrate; forming a source and a drain region in a predetermined region by performing ion implantation; removing the nitride film; depositing a high melting point metal on the substrate; And reacting the high melting point metal with the portion containing Si in contact with the high melting point metal to form a high melting point metal silicide. 제1항에 있어서, 상기 폴리실리콘층은 로드록 시스템을 이용하여 형성하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the polysilicon layer is formed using a loadlock system. 제1항에 있어서, 상기 질화막에 의해 상기 게이트전극이 불순물들로부터 보호되는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the gate electrode is protected from impurities by the nitride film. 제1항에 있어서, 상기 고융점금속은 Ti인 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the high melting point metal is Ti. 제1항에 있어서, 상기 Si이 포함된 부분은 상기 게이트전극표면과 상기 소오스및 드레인영역임을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the Si-containing portion comprises the gate electrode surface and the source and drain regions. 제1항에 있어서, 상기 열처리는 RTA에 의해 행하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the heat treatment is performed by RTA.
KR1019960023647A 1996-06-25 1996-06-25 Method for fabricating semiconductor device KR100390817B1 (en)

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JPS63146468A (en) * 1986-07-28 1988-06-18 Oki Electric Ind Co Ltd Manufacture of semiconductor device
KR950013131B1 (en) * 1989-11-03 1995-10-25 삼성전자주식회사 Method of crealit card check using video terminal
JP3277434B2 (en) * 1994-07-28 2002-04-22 ソニー株式会社 Method for manufacturing transistor

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