KR980006258A - Manufacturing process of BCDMOS - Google Patents

Manufacturing process of BCDMOS Download PDF

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Publication number
KR980006258A
KR980006258A KR1019960024420A KR19960024420A KR980006258A KR 980006258 A KR980006258 A KR 980006258A KR 1019960024420 A KR1019960024420 A KR 1019960024420A KR 19960024420 A KR19960024420 A KR 19960024420A KR 980006258 A KR980006258 A KR 980006258A
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region
conductive
well
forming
exposed
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KR1019960024420A
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Korean (ko)
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KR100188121B1 (en
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이순학
전창기
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 BCDMOS(Bipolar + CMOS + Double Fiffused MOS)의 제조 공정에 관한 것으로 특히, 웨이퍼의 소정 영역에 제1, 제2 전도성 웰영역을 인접하게 형성시키고 상기 제2전도성 웰의 전체 영역과 제1전도성 웰 영역의 중심부에 대응하는 소정의 영역 및 임의의 특정 영역의 중심부와 주변에 대응하는 부분 이외의 영역이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제1공정과; 특정 영역에 해당하는 부분만을 노출시키도록 포토 레지스터를 형성하고 노출된 영역에 제1전도성 이온을 주사하여 제2의 제1전도성형 웰 영역을 생성시키는 제2공정과; 제2공정에서 형성되어진 포토 레지스터를 제거하여 제1공정에서 생성되어진 제1전도성형 웰영역을 노출시킨 후 제2전도성 양이온을 주사하여 각각의 제1전도성형 웰영역에 제2전도성 양이온 영역을 생성시키는 제3공정과; 제2공정에서 생성되어진 제2의 제1전도성형 웰 영역의 중심부와 제1공정에서 생성되어진 제2전도성형 웰영역에서 중심부를 제외한 영역만이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제4공정과; 제4공정을 통해 노출되어진 영역에 제2전도성 양이온을 주사하여 해당 영역에 제2전도성 양이온 영역을 생성시키는 제5공정; 및 각 전도성 영역에 금속배선을 형성하는 제6공정을 포함하는 것을 특징으로 하는 비씨디 모스의 제조공정을 제공하면 종전의 제조공정에 비하여 사진작업을 줄일 수 있어 소자 특성 변화를 최소화하고 미세 공정의 실현이 가능해져 칩 사이즈가 작아지며 동작저항도 줄일 수 있다.The present invention relates to a manufacturing process of BCDMOS (Bipolar + CMOS + Double Fiffused MOS), and more particularly, to a method of manufacturing a semiconductor device, in which first and second conductive well regions are formed adjacent to a predetermined region of a wafer, A first step of performing a photolithography process and an etching process so that a predetermined region corresponding to the central portion of the conductive well region and a region other than a portion corresponding to the periphery of the center portion and any peripheral region of the specific region are exposed; A second step of forming a photoresist so as to expose only a portion corresponding to a specific region and scanning the exposed region with a first conductive ion to form a second first conductive formed well region; The photoresist formed in the second step is removed to expose the first conductive formed well region generated in the first step and then the second conductive cation is injected to generate a second conductive cation region in each of the first conductive formed well regions ; A photolithography process and an etch process are performed so that only the center portion of the second first conductive formed well region generated in the second process and the region except the central portion in the second conductive formed well region generated in the first process are exposed. 4 process; A fifth step of injecting a second conductive cation into a region exposed through a fourth step to generate a second conductive cation region in the region; And a sixth step of forming a metal interconnection in each conductive region. This can reduce the number of photolithography operations compared to the conventional manufacturing process, minimizing changes in device characteristics, The chip size can be reduced and the operation resistance can be reduced.

Description

비씨디 모스(BCDMOS)의 제조 공정Manufacturing process of BCDMOS

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 6도는 본 발명에 따른 BCDMOS의 제작 공정 예시도6 is a diagram illustrating a manufacturing process of a BCDMOS according to the present invention;

Claims (9)

웨이퍼의 소정 영역에 제1, 제2 전도성 웰영역을 인접하게 형성시키고 상기 제2전도성 웰의 전체 영역과 제1전도성 웰 영역의 중심부에 대응하는 소정의 영역 및 임의의 특정 영역의 중심부와 주변에 대응하는 부분 이외의 영역이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제1공정과; 상기 특정 영역에 해당하는 부분만을 노출시키도록 포토 레지스터를 형성하고 노출된 영역에 제1전도성 이온을 주사하여 제2의 제1전도성형 웰 영역을 생성시키는 제2공정과; 상기 제2공정에서 형성되어진 포토 레지스터를 제거하여 제1공정에서 생성되어진 제1전도성형 웰영역을 노출시킨 후 제2전도성 양이온을 주사하여 각각의 제1전도성형 웰영역에 제2전도성 양이온 영역을 생성시키는 제3공정과; 상기 제2공정에서 생성되어진 제2의 제1전도성형 웰 영역의 중심부와 제1공정에서 생성되어진 제2전도성형 웰영역에서 중심부를 제외한 영역만이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제4공정과; 제4공정을 통해 노출되어진 영역에 제2전도성 양이온을 주사하여 해당 영역에 제2전도성 양이온 영역을 생성시키는 제5공정; 및 각 전도성 영역에 금속배선을 형성하는 제6공정을 포함하는 것을 특징으로 하는 비씨디 모스의 제조공정The first and second conductive well regions are formed adjacent to each other in a predetermined region of the wafer and a predetermined region corresponding to the entire region of the second conductive well and the center portion of the first conductive well region, A first step of performing a photographic operation and an etching process so that a region other than the corresponding portion is exposed; Forming a photoresist so as to expose only a portion corresponding to the specific region and scanning the exposed region with a first conductive ion to form a second first conductive formed well region; The photoresist formed in the second step is removed to expose the first conductive formed well region generated in the first step and then the second conductive cation is injected to form a second conductive cation region in each first conductive formed well region ; A photolithography process and an etching process are performed so that only the center portion of the second first conductive formed well region generated in the second process and the region except the center portion in the second conductive formed well region generated in the first process are exposed A fourth step; A fifth step of injecting a second conductive cation into a region exposed through a fourth step to generate a second conductive cation region in the region; And a sixth step of forming a metal interconnection in each of the conductive regions. 제1항에 있어서, 상기 제1전도성은 P형인 것을 특징으로 하는 비씨디 모스의 제조공정The method according to claim 1, wherein the first conductivity is P-type 제1항에 있어서, 상기 제2전도성은 N형인 것을 특징으로 하는 비씨디 모스의 제조공정The method according to claim 1, wherein the second conductivity is N-type 제1항에 있어서, 상기 제1전도성 양이온은 P+형 이온인 것을 특징으로 하는 비씨디 모스의 제조공정The process according to claim 1, wherein the first conductive cation is a P + -type ion 제1항에 있어서, 상기 제2전도성 양이온은 N+형 이온인 것을 특징으로 하는 비씨디 모스의 제조공정The method according to claim 1, wherein the second conductive cation is an N + -type ion 제1항에 있어서, 상기 제1공정은 웨이퍼의 소정 영역에 제1 전도성형 웰과 제2전도성형 웰을 인접하게 형성시키는 제1단계와; 상기 제1전도성형 웰과 제2전도성형 웰의 사이에 그리고 다른 웨이퍼 영역에 특정 패턴에 따른 로코스를 형성하는 제2단계와; 상기 로코스가 차지하는 영역 이외의에 소정의 두께로 산화막을 형성시키는 제3단계와; 전제의 웨이퍼 영역에 대하여 순차적으로 게이트 폴리와 산화막과 질하막 및 포토 레지스터를 증착하는 제4단계와; 증착되어진 포토 레지스터의 대하여 소정 패턴의 마스크를 사용한 사진 작업을 통한 제1전도성형 웰의 전체 영역과 제2전도성형 웰 영역의 중심부에 대응하는 소정의 영역 및 임의의 특정 영역에 대응하는 부분만을 안정화시키는 제5단계; 및 제5단계를 통하여 안정화된 부분 이외의 영역에 대하여 상기 게이트 폴리부분까지 식각하는 제6단계를 포함하는 것을 특징으로 하는 비씨디모스의 제조공정2. The method of claim 1, wherein the first step comprises: a first step of forming a first conduction-forming well and a second conduction-forming well adjacent to a predetermined region of the wafer; A second step of forming a locus according to a specific pattern between the first conduction forming well and the second conducting well and in another wafer region; A third step of forming an oxide film to a predetermined thickness in a region other than the region occupied by the locus; A fourth step of sequentially depositing the gate poly, the oxide film, the sub-film and the photoresist on the entire wafer area; Only the portion corresponding to the entire region of the first conductive forming well and the predetermined region corresponding to the central portion of the second conductive formed well region and the specific region through photolithography using the mask of the predetermined pattern with respect to the photoresist deposited is stabilized Fifth step; And a sixth step of etching the gate poly part to an area other than the stabilized part through a fifth step 제2항에 있어서, 상기 제3단계에서 형성되는 산호막의 두께는 상기 로코스의 두께에 비하여 상대적으로 얇은 것을 특징으로 하는 비씨디 모스의 제조공정3. The method according to claim 2, wherein the thickness of the coral film formed in the third step is relatively thinner than the thickness of the LOCOS. 제2항에 있어서, 상기 제4단계에서 증착되는 산호막과 질화막의 두께는 게이트 폴리의 두께에 비하여 상대적으로 얇은 것을 특징으로 하는 비씨디 모스의 제조공정3. The method according to claim 2, wherein the thickness of the coral film and the nitride film deposited in the fourth step is relatively thinner than the thickness of the gate poly, 제1항 또는 제6항에 있어서, 상기 제3공정이후 상기 제1공정의 제6단계를 통하여 노출되어진 산화막을 열처리하여 해당 산화막을 좀더 두껍게 변형시킨 후 제4공정으로 진행하는 열처리 공정을 포함하는 것을 특징으로 하는 비씨디모스의 제조공정The method of claim 1 or 6, further comprising, after the third step, performing a heat treatment on the oxide film exposed through the sixth step of the first step to further thicken the oxide film, and then proceeding to a fourth step A process for producing B-Cydimose
KR1019960024420A 1996-06-27 1996-06-27 Method of manufacturing bcdmos KR100188121B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437828B1 (en) * 2001-12-18 2004-06-30 주식회사 하이닉스반도체 method for manufacturing of BCD device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412539B1 (en) * 2001-07-24 2003-12-31 한국전자통신연구원 BCD device and method of manufacturing the same
KR100523053B1 (en) * 2002-10-31 2005-10-24 한국전자통신연구원 Smart power device built-in SiGe HBT and fabrication method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437828B1 (en) * 2001-12-18 2004-06-30 주식회사 하이닉스반도체 method for manufacturing of BCD device

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