KR980006258A - Manufacturing process of BCDMOS - Google Patents
Manufacturing process of BCDMOS Download PDFInfo
- Publication number
- KR980006258A KR980006258A KR1019960024420A KR19960024420A KR980006258A KR 980006258 A KR980006258 A KR 980006258A KR 1019960024420 A KR1019960024420 A KR 1019960024420A KR 19960024420 A KR19960024420 A KR 19960024420A KR 980006258 A KR980006258 A KR 980006258A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- conductive
- well
- forming
- exposed
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract 21
- 150000001768 cations Chemical class 0.000 claims abstract 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 6
- 238000000206 photolithography Methods 0.000 claims abstract 5
- 238000005530 etching Methods 0.000 claims abstract 4
- 150000002500 ions Chemical class 0.000 claims abstract 4
- 239000002184 metal Substances 0.000 claims abstract 2
- 235000014653 Carica parviflora Nutrition 0.000 claims 2
- 241000243321 Cnidaria Species 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 BCDMOS(Bipolar + CMOS + Double Fiffused MOS)의 제조 공정에 관한 것으로 특히, 웨이퍼의 소정 영역에 제1, 제2 전도성 웰영역을 인접하게 형성시키고 상기 제2전도성 웰의 전체 영역과 제1전도성 웰 영역의 중심부에 대응하는 소정의 영역 및 임의의 특정 영역의 중심부와 주변에 대응하는 부분 이외의 영역이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제1공정과; 특정 영역에 해당하는 부분만을 노출시키도록 포토 레지스터를 형성하고 노출된 영역에 제1전도성 이온을 주사하여 제2의 제1전도성형 웰 영역을 생성시키는 제2공정과; 제2공정에서 형성되어진 포토 레지스터를 제거하여 제1공정에서 생성되어진 제1전도성형 웰영역을 노출시킨 후 제2전도성 양이온을 주사하여 각각의 제1전도성형 웰영역에 제2전도성 양이온 영역을 생성시키는 제3공정과; 제2공정에서 생성되어진 제2의 제1전도성형 웰 영역의 중심부와 제1공정에서 생성되어진 제2전도성형 웰영역에서 중심부를 제외한 영역만이 노출될 수 있도록 사진작업과 식각공정을 수행하는 제4공정과; 제4공정을 통해 노출되어진 영역에 제2전도성 양이온을 주사하여 해당 영역에 제2전도성 양이온 영역을 생성시키는 제5공정; 및 각 전도성 영역에 금속배선을 형성하는 제6공정을 포함하는 것을 특징으로 하는 비씨디 모스의 제조공정을 제공하면 종전의 제조공정에 비하여 사진작업을 줄일 수 있어 소자 특성 변화를 최소화하고 미세 공정의 실현이 가능해져 칩 사이즈가 작아지며 동작저항도 줄일 수 있다.The present invention relates to a manufacturing process of BCDMOS (Bipolar + CMOS + Double Fiffused MOS), and more particularly, to a method of manufacturing a semiconductor device, in which first and second conductive well regions are formed adjacent to a predetermined region of a wafer, A first step of performing a photolithography process and an etching process so that a predetermined region corresponding to the central portion of the conductive well region and a region other than a portion corresponding to the periphery of the center portion and any peripheral region of the specific region are exposed; A second step of forming a photoresist so as to expose only a portion corresponding to a specific region and scanning the exposed region with a first conductive ion to form a second first conductive formed well region; The photoresist formed in the second step is removed to expose the first conductive formed well region generated in the first step and then the second conductive cation is injected to generate a second conductive cation region in each of the first conductive formed well regions ; A photolithography process and an etch process are performed so that only the center portion of the second first conductive formed well region generated in the second process and the region except the central portion in the second conductive formed well region generated in the first process are exposed. 4 process; A fifth step of injecting a second conductive cation into a region exposed through a fourth step to generate a second conductive cation region in the region; And a sixth step of forming a metal interconnection in each conductive region. This can reduce the number of photolithography operations compared to the conventional manufacturing process, minimizing changes in device characteristics, The chip size can be reduced and the operation resistance can be reduced.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제 6도는 본 발명에 따른 BCDMOS의 제작 공정 예시도6 is a diagram illustrating a manufacturing process of a BCDMOS according to the present invention;
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024420A KR100188121B1 (en) | 1996-06-27 | 1996-06-27 | Method of manufacturing bcdmos |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024420A KR100188121B1 (en) | 1996-06-27 | 1996-06-27 | Method of manufacturing bcdmos |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980006258A true KR980006258A (en) | 1998-03-30 |
KR100188121B1 KR100188121B1 (en) | 1999-06-01 |
Family
ID=19463820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960024420A KR100188121B1 (en) | 1996-06-27 | 1996-06-27 | Method of manufacturing bcdmos |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100188121B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100437828B1 (en) * | 2001-12-18 | 2004-06-30 | 주식회사 하이닉스반도체 | method for manufacturing of BCD device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100412539B1 (en) * | 2001-07-24 | 2003-12-31 | 한국전자통신연구원 | BCD device and method of manufacturing the same |
KR100523053B1 (en) * | 2002-10-31 | 2005-10-24 | 한국전자통신연구원 | Smart power device built-in SiGe HBT and fabrication method of the same |
-
1996
- 1996-06-27 KR KR1019960024420A patent/KR100188121B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100437828B1 (en) * | 2001-12-18 | 2004-06-30 | 주식회사 하이닉스반도체 | method for manufacturing of BCD device |
Also Published As
Publication number | Publication date |
---|---|
KR100188121B1 (en) | 1999-06-01 |
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