KR980006253A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR980006253A
KR980006253A KR1019960025771A KR19960025771A KR980006253A KR 980006253 A KR980006253 A KR 980006253A KR 1019960025771 A KR1019960025771 A KR 1019960025771A KR 19960025771 A KR19960025771 A KR 19960025771A KR 980006253 A KR980006253 A KR 980006253A
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KR
South Korea
Prior art keywords
nitride film
film
semiconductor device
oxide film
forming
Prior art date
Application number
KR1019960025771A
Other languages
Korean (ko)
Inventor
김근태
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025771A priority Critical patent/KR980006253A/en
Publication of KR980006253A publication Critical patent/KR980006253A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로서, LDD구조를 가지는 반도체소자에서 상기 LDD구조를 산화막과 질화막의 이중 LDD 스페이서를 사용하여 형성하고, 외측의 질화막 패턴으로된 스페이서 부분을 제거한후, SAC 공정을 진행하며 콘택 공정 여유도가 증가되고, 게이트전극 손상도 방지되어 공성수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a method of manufacturing a semiconductor device, in which a semiconductor device having an LDD structure is formed by forming the LDD structure using a double LDD spacer including an oxide film and a nitride film, removing a portion of a spacer having an outer nitride film pattern, The contact process margin is increased, damage to the gate electrode is prevented, and sintered yield and reliability of device operation can be improved.

Description

반도체소자의 제조방법Method of manufacturing semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 2a도 내지 제 2f도는 본 발명에 따른 반도체소자의 제조 공정도FIGS. 2 (a) to 2 (f) are diagrams showing a manufacturing process of a semiconductor device according to the present invention

Claims (5)

반도체 기판상에 게이트 산화막을 형성하는 공정과, 상기 게이트 산호막상에 마스크 산화막과 중첩되어 있는 게이트전극을 형성하는 공정과, 상기 게이트전극 양측의 반도체기판에 저농도 불순물 영역을 형성하는 공정과, 상기 구조의 전표면에 스페이서용 산화막과 질화막을 순차적으로형성하는 공정과, 상기 질화막과 산화막을 순차적으로 전면 식각하여 산화막 및 질화막 패턴으로된 스페이서를 셩성하는 공정과, 상기 스페이서 양측의 반도체기판에 소오스/드레인 영역을 형성하는 공정과, 상기 질화막 스페이서를 제거하는 공정과, 상기 구조의 전표면에 질화막을 형성하는 공정과, 상기 질화막 상에 층간절연막을 형성하는 고정과, 상기 반도체기판에서 콘택으로 예정되어 있는 상측의 층간절연막을 제거하여 질화막을 노출시키는 공정과, 상기 질화막을 제거하여 콘택홀을 형성하는 공정을 구비하는 반도체소자의 제조방법A step of forming a gate oxide film on the semiconductor substrate; a step of forming a gate electrode overlapping the mask oxide film on the gate oxide film; a step of forming a low concentration impurity region in the semiconductor substrate on both sides of the gate electrode; A step of sequentially etching the nitride film and the oxide film to form a spacer made of an oxide film and a nitride film pattern on the entire surface of the spacer, a step of sequentially etching the nitride film and the oxide film to form a spacer having a source / A step of forming a nitride film on the entire surface of the structure; a step of forming an interlayer insulating film on the nitride film; Removing the upper interlayer insulating film to expose the nitride film, And removing the nitride film to form a contact hole. 제1항에 있어서, 상기 게이트전극을 다결정 실리콘층과 W 실리사이드 및 마스트 산호막 패턴의 적층 구조로 형성하는 것을 특징으로 하는 반도체소자의 제조방법The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is formed in a laminated structure of a polycrystalline silicon layer, a W silicide, and a mast corundum film pattern 제1항에 있어서, 상기 질화막 스페이서의 제거를 인산 용액을 사용한 습식식각 방법으로 실시하는 것을 특징으로 하는 반도체소자의 제조방법The method for manufacturing a semiconductor device according to claim 1, wherein the removal of the nitride film spacer is performed by a wet etching method using a phosphoric acid solution 제1항에 있어서, 상기 SAC를 질화막의 하부에 스트레스 방지용으로 산화막을 개재시키는 것을 특징으로 하는 반도체소자의 제조방법The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film is interposed between the SAC and the nitride film for preventing stress 제1항에 있어서, 상기 SAC용 질화막을 200-1000A 두께로 형성하는 것을 특징으로 하는 반도체소자의 제조방법The method for manufacturing a semiconductor device according to claim 1, wherein the nitride film for SAC is formed to a thickness of 200-1000 A
KR1019960025771A 1996-06-29 1996-06-29 Method of manufacturing semiconductor device KR980006253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025771A KR980006253A (en) 1996-06-29 1996-06-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025771A KR980006253A (en) 1996-06-29 1996-06-29 Method of manufacturing semiconductor device

Publications (1)

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KR980006253A true KR980006253A (en) 1998-03-30

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KR1019960025771A KR980006253A (en) 1996-06-29 1996-06-29 Method of manufacturing semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100312979B1 (en) * 1998-06-29 2002-01-17 박종섭 Method for fabricating semiconductor device
KR100348222B1 (en) * 1999-12-28 2002-08-09 주식회사 하이닉스반도체 A method for forming a contact line of a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100312979B1 (en) * 1998-06-29 2002-01-17 박종섭 Method for fabricating semiconductor device
KR100348222B1 (en) * 1999-12-28 2002-08-09 주식회사 하이닉스반도체 A method for forming a contact line of a semiconductor device

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