KR980005425A - 반도체장치의 얕은 접합(shallow junction)층 형성방법 - Google Patents

반도체장치의 얕은 접합(shallow junction)층 형성방법 Download PDF

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KR980005425A
KR980005425A KR1019960022599A KR19960022599A KR980005425A KR 980005425 A KR980005425 A KR 980005425A KR 1019960022599 A KR1019960022599 A KR 1019960022599A KR 19960022599 A KR19960022599 A KR 19960022599A KR 980005425 A KR980005425 A KR 980005425A
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forming
polysilicon
layer
shallow junction
plug
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KR1019960022599A
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KR100190047B1 (ko
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고광만
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치의 얕은 접합(shallow junction)층 형성방법에 관해 개시한다 본 발명에 의한 얕은 접합층 형성방법은 주입되는 이온들에 대해서 완충층으로써 사용하는 폴리 실리콘 플러그를 성장방법으로 형성하지 않고 적층방법으로 형성한다. 따라서 본 발명에 의한 얕은 접합(shallow junction)층 형성방법은 공정을 안정적으로 진행할 수 있고, 웨이퍼에 무리를 주지 않으므로 디바이스의 신뢰성도 높일 수 있다. 또한, 종래의 플러그 성장법은 플러그의 두께를 조절하기가 매우 어렵다. 반면, 본 발명은 평탄화 공정이나 에치 백공정을통해서 플러그의 두께 조절이 쉬우므로 이온들의 Rp조절을 쉽게할 수 있다. 따라서 접합층의 깊이를 조절할 수 있고 얕은 접합층도 쉽게 형성할 수 있다.

Description

반도체장치의 얕은 접합(shallow junction)층 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 내지 제4도는 본 발명의 일실시예에 의한 반도체장치의 얕은 접합 (shallow junction)층을 형성방법을 단계별로 나타낸 도면들이다.

Claims (8)

  1. 반도체기판에 필드산화막을 형성하여 활성영역과 비 활성영역을 구분하는 단계; 상기 활성영역 상에 스페이서를 구비하는 게이트전극을 형성하는 단계; 상기 게이트전극을 포함하는 반도체기판 전면에 폴리 실리콘층을 적층하는 단계; 상기 게이트 전극사이에 일정 두께를 갖는 폴리실리콘 플러그를 형성하는 단계; 및 상기 결과물 전면에 이온주입을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  2. 제1항에 있어서, 상기 폴리실리콘 플러그를 상기 이온주입에 대해서 완충층으로 사용하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  3. 제1항에 상기 폴리 실리콘 플러그를 형성하는 단계에서 상기 스페이서의 계면을 식각종말점으로 이용하는 것을 특징으로 하는 반도체장치의 얕은 접합 (shallow junction)층 형성방법.
  4. 제1항에 있어서, 상기 스페이서는 상기 폴리실리콘층과 식각선택비가 있는 재료를 사용하여 형성하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  5. 제4항에 있어서, 상기 폴리실리콘층과 식각선택비가 있는 재료로서는 나이트라이드나 산화막중에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  6. 제1항에 있어서, 상기 폴리실리콘 플러그는 상기 폴리실리콘층을 평탄화함으로써 형성되는데 상기 평탄화를 위해 CMP방법을 사용하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  7. 제1항에 있어서, 상기 폴리실리콘 플러그는 상기 폴리실리콘층의 전면을 건식으로 에치 백하여 형성하는 것을 특징으로 하는 반도체장치의 얕은 접합(shallow junction)층 형성방법.
  8. 제1항에 있어서, 상기 폴리실리콘 플러그는 상기 주입되는 이온의 비정거리 (Rp)를 조절하는 수단으로 사용되는 것을 특징으로 하는 반도체장치의 얕은 접합 (shallow junction)층 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960022599A 1996-06-20 1996-06-20 반도체장치의 얕은 접합층 형성방법 KR100190047B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019960022599A KR100190047B1 (ko) 1996-06-20 1996-06-20 반도체장치의 얕은 접합층 형성방법

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Application Number Priority Date Filing Date Title
KR1019960022599A KR100190047B1 (ko) 1996-06-20 1996-06-20 반도체장치의 얕은 접합층 형성방법

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KR980005425A true KR980005425A (ko) 1998-03-30
KR100190047B1 KR100190047B1 (ko) 1999-06-01

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KR20000039964A (ko) * 1998-12-16 2000-07-05 김영환 반도체장치의 플러그 형성방법

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