KR980005063A - Thermal redundancy circuit - Google Patents
Thermal redundancy circuit Download PDFInfo
- Publication number
- KR980005063A KR980005063A KR1019960026514A KR19960026514A KR980005063A KR 980005063 A KR980005063 A KR 980005063A KR 1019960026514 A KR1019960026514 A KR 1019960026514A KR 19960026514 A KR19960026514 A KR 19960026514A KR 980005063 A KR980005063 A KR 980005063A
- Authority
- KR
- South Korea
- Prior art keywords
- redundancy circuit
- cell array
- memory cell
- address signal
- thermal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
본 발명은 반도체 제조 과정에서, 메모리 제품 설계시에 반도체 장치의 불량 셀을 대체하기 위한 열(column) 리던던시 회로에 관한 것으로, 메모리 셀 어레이와, 상기 메모리 셀 어레이의 셀을 선택하기 위한 글로벌 워드라인과, 상기 메모리 셀 어레이의 셀에 정보를 입출력하기 위하여 열(column) 어드레스 신호 및 행(row) 어드레스 신호를 사용하여 비트라인을 선택하도록 구성한 것을 특징으로 하며, 작은 면적에 열 리던던시 회로를 구현함으로써 동일한 면적에 종래의 방법에 비해 더 많은 리페어 셀을 배치할 수 있기 때문에 수율 향상에 효과적이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column redundancy circuit for replacing a defective cell of a semiconductor device in the course of designing a memory product in a semiconductor manufacturing process and includes a memory cell array and a global word line for selecting cells of the memory cell array And a bit line is selected using a column address signal and a row address signal for inputting / outputting information to / from the cell of the memory cell array. By implementing a thermal redundancy circuit with a small area Since more repair cells can be arranged in the same area as compared with the conventional method, it is effective in improving the yield.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제4도는 본 발명에 따른 열 리던던시 회로의 구성 예시도.FIG. 4 is a diagram showing a configuration example of a thermal redundancy circuit according to the present invention; FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960026514A KR100233287B1 (en) | 1996-06-29 | 1996-06-29 | Semiconductor memory device having a repair column structure to reduce chip size |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960026514A KR100233287B1 (en) | 1996-06-29 | 1996-06-29 | Semiconductor memory device having a repair column structure to reduce chip size |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980005063A true KR980005063A (en) | 1998-03-30 |
KR100233287B1 KR100233287B1 (en) | 1999-12-01 |
Family
ID=19465189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960026514A KR100233287B1 (en) | 1996-06-29 | 1996-06-29 | Semiconductor memory device having a repair column structure to reduce chip size |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100233287B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100447262B1 (en) * | 1999-12-28 | 2004-09-07 | 주식회사 하이닉스반도체 | A method for layout a rest cell of a memory device |
-
1996
- 1996-06-29 KR KR1019960026514A patent/KR100233287B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100447262B1 (en) * | 1999-12-28 | 2004-09-07 | 주식회사 하이닉스반도체 | A method for layout a rest cell of a memory device |
Also Published As
Publication number | Publication date |
---|---|
KR100233287B1 (en) | 1999-12-01 |
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