KR970051430A - How to implement low redundancy - Google Patents
How to implement low redundancy Download PDFInfo
- Publication number
- KR970051430A KR970051430A KR1019950057159A KR19950057159A KR970051430A KR 970051430 A KR970051430 A KR 970051430A KR 1019950057159 A KR1019950057159 A KR 1019950057159A KR 19950057159 A KR19950057159 A KR 19950057159A KR 970051430 A KR970051430 A KR 970051430A
- Authority
- KR
- South Korea
- Prior art keywords
- word line
- redundancy
- implementation method
- word
- fuse box
- Prior art date
Links
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
재생 수율 하락(repair yield down)을 개선하기 위한 리던던시 구현방법을 개시한다.Disclosed is a method of implementing redundancy to improve repair yield down.
반도체 메모리의 어레이 블록의 셀에 페일이 발생하면, 구비된 더미셀(dummy cell)로 대체하는 리던던시 구현 방법에 있어서, 재생되는 리던던시 스페어 워드라인의 단위를, 통상의 디코더에서 인에이블될 수 있는 워드라인 단위의 1, 1/2, 1/4, 1/8…로 구현한 것을 특징으로 하는 리던던시 구현 방법을 제공한다.When a failure occurs in a cell of an array block of a semiconductor memory, a redundancy implementation method of replacing a dummy cell with a word, wherein a unit of a redundancy spare word line to be reproduced can be enabled in a conventional decoder. 1, 1/2, 1/4, 1/8 in line units. It provides a redundancy implementation method characterized in that implemented as.
상기 인에이블될 수 있는 워드라인 단위는 퓨즈 상자내에 워드라인 어드레스에 해당되는 퓨즈를 추가로 구비하고, 이들의 제어는 워드라인 어드레스에 종속되게 한다.The enabled word line unit further includes a fuse corresponding to the word line address in the fuse box, and their control is subject to the word line address.
따라서, 본 발명에 의하면 전체 퓨즈상자에 2개의 퓨즈를 추가시켜 종래 기술에서 문제되었던 수율 하락을 반으로 줄이는 방법을 구현할 수 있다.Therefore, according to the present invention, by adding two fuses to the entire fuse box, it is possible to implement a method of reducing the yield drop, which has been a problem in the related art, in half.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 의해 리던던시 워드라인 선택적으로 인에이블 및 디져블 시킬 수 있도록 리던던시 디코더를 제어하는 퓨즈를 구비한 회로도이다.2 is a circuit diagram having a fuse controlling a redundancy decoder to selectively enable and disable redundancy word lines according to the present invention.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057159A KR970051430A (en) | 1995-12-26 | 1995-12-26 | How to implement low redundancy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950057159A KR970051430A (en) | 1995-12-26 | 1995-12-26 | How to implement low redundancy |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970051430A true KR970051430A (en) | 1997-07-29 |
Family
ID=66618981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950057159A KR970051430A (en) | 1995-12-26 | 1995-12-26 | How to implement low redundancy |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970051430A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447262B1 (en) * | 1999-12-28 | 2004-09-07 | 주식회사 하이닉스반도체 | A method for layout a rest cell of a memory device |
-
1995
- 1995-12-26 KR KR1019950057159A patent/KR970051430A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447262B1 (en) * | 1999-12-28 | 2004-09-07 | 주식회사 하이닉스반도체 | A method for layout a rest cell of a memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3598119B2 (en) | Redundant decoder | |
| US5349556A (en) | Row redundancy circuit sharing a fuse box | |
| KR940016279A (en) | Semiconductor memory device with improved redundancy efficiency | |
| KR950015398A (en) | Low Redundancy Circuit and Method in Semiconductor Memory Device with Double Low Decoder | |
| JP3157753B2 (en) | Semiconductor memory circuit | |
| JPS6329360B2 (en) | ||
| KR960002796A (en) | Column Redundancy Device for Semiconductor Devices | |
| KR970012781A (en) | Semiconductor memory device with column redundancy circuit | |
| KR940010113A (en) | Fault Relief Circuit in Semiconductor Memory Device | |
| US7218558B2 (en) | Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks | |
| KR970012708A (en) | Integrated semiconductor memory device | |
| KR960002368A (en) | Semiconductor Memory Device with Redundancy Function | |
| KR100468315B1 (en) | Repair circuit | |
| KR950009744A (en) | Semiconductor memory | |
| KR970051430A (en) | How to implement low redundancy | |
| KR970051427A (en) | Semiconductor Memory Devices with Redundancy Efficiency | |
| KR100266624B1 (en) | Memory redundancy circuit | |
| US6680857B2 (en) | Unit-architecture with implemented limited bank-column-select repairability | |
| KR970051446A (en) | Redundancy Roo Decoder Circuit | |
| JP2859780B2 (en) | Semiconductor storage device | |
| KR950020754A (en) | Column redundancy circuit | |
| KR960015902A (en) | Device for repairing semiconductor memory device | |
| KR100284292B1 (en) | Semiconductor memory apparatus | |
| KR960035268A (en) | Spare decoder circuit to repair DRAM with defective cells | |
| KR970051419A (en) | Low Redundancy Circuit in Semiconductor Memory Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |