KR980004038A - CRC calculation method of multi-bit - Google Patents
CRC calculation method of multi-bit Download PDFInfo
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- KR980004038A KR980004038A KR1019960022066A KR19960022066A KR980004038A KR 980004038 A KR980004038 A KR 980004038A KR 1019960022066 A KR1019960022066 A KR 1019960022066A KR 19960022066 A KR19960022066 A KR 19960022066A KR 980004038 A KR980004038 A KR 980004038A
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- crc
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- calculation method
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- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
본 발명은 멀티 비트 CRC(Cyclic Redundancy Check Code : 순회 용장부호)여산 방법에 관한 것으로서, 특히 멀티 비트 또는 바이트 단위의 연상을 할 수 있는 멀티 비티의 CRC 연산 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bit Cyclic Redundancy Check Code (CRC) calculation method, and more particularly, to a multi-bit CRC calculation method capable of multi-bit or byte association.
본 발명의 목적을 위하여 CRC 레지스터의 값을 초기화하는 제1단계, 입력되는 n비트 값과 제1단계에서의 CRC 레지스터의 k비트 값을 n-k만큼 시프트하여 배타적 OR하는 제2단계, 제2단계에서 구한 각 비트에 대해 x16+k/g(x) 의 생성 다항식(Rg(x))를 구하는 제3단계, 제3단계에서의 생성 다항식을 15부터 0까지 비트에 대해 정리하여 CRC 값을 구하는 제4단계를 포함한다.In the first step of initializing the value of the CRC register for the purpose of the present invention, the second step of the exclusive OR by shifting the input n-bit value and the k-bit value of the CRC register in the first step by nk The CRC value is obtained by arranging the generation polynomial (Rg (x)) of x 16 + k / g (x) for each bit obtained by arranging the generation polynomial in the third step from 15 to 0 bits. A fourth step is included.
본 발명에 의하면 바이트 또는 워드 단위의 CRC 연산을 단일 클럭으로 수행함으로서 오차 정정 속도가 8배 빠른 멀티 비트의 CRC 연산이 가능한 잇점이 있다.According to the present invention, a multi-bit CRC operation having an eight times faster error correction speed can be performed by performing a CRC operation in a byte or word unit with a single clock.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 종래의 비트 단위의 CRC 연산 정치를 보이는 블럭도이다.1 is a block diagram showing a conventional CRC operation stationary bit unit.
제2도는 본 발명에 따른 멀티 비트의 CRC 연산 방법의 플로우차트이다.2 is a flowchart of a multi-bit CRC calculation method according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019960022066A KR980004038A (en) | 1996-06-18 | 1996-06-18 | CRC calculation method of multi-bit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019960022066A KR980004038A (en) | 1996-06-18 | 1996-06-18 | CRC calculation method of multi-bit |
Publications (1)
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KR980004038A true KR980004038A (en) | 1998-03-30 |
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Family Applications (1)
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KR1019960022066A KR980004038A (en) | 1996-06-18 | 1996-06-18 | CRC calculation method of multi-bit |
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KR (1) | KR980004038A (en) |
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1996
- 1996-06-18 KR KR1019960022066A patent/KR980004038A/en not_active Application Discontinuation
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