KR970078023A - Timer / counter circuit - Google Patents
Timer / counter circuit Download PDFInfo
- Publication number
- KR970078023A KR970078023A KR1019960016450A KR19960016450A KR970078023A KR 970078023 A KR970078023 A KR 970078023A KR 1019960016450 A KR1019960016450 A KR 1019960016450A KR 19960016450 A KR19960016450 A KR 19960016450A KR 970078023 A KR970078023 A KR 970078023A
- Authority
- KR
- South Korea
- Prior art keywords
- multiplexer
- output
- timer
- clock
- counter circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
- H03K21/406—Synchronisation of counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
Abstract
본 발명은 그 회로에 대한 테스트 시간을 크게 줄여 테스트의 효율성과 양산성이 향상된 타이머/카운터 회로에 관한 것으로, 소정의 클록 선택신호에 따라 다수의 클록 중에서 하나를 선택하여 출력하는 멀티플렉서(Multiflexer)와; 상기 멀티플렉서에서 출력되는 클록에 동기되어 카운트하는 카운터부와; 소정의 선택신호에 따라 상기 멀티플렉서에서 출력되는 클록을 선택하여 포트부로 출력하는 멀티플렉서출력 선택부로 구성되는 것을 특징으로 한다. 이와 같이 구성된 본 발명 타이머/카운터 회로는 소정의 선택신호에 따라 멀티플렉서에서 출력되는 클럭을 선택하여 출력하는 멀티플렉서 출력선택부가 그 출력을 포트부를 통해 테스트 장치로 전달함으로써, 멀티플렉서의 선택동작에 대한 테스트를 빠른 시간 안에 수행할 수 있는 효과가 있다.The present invention relates to a timer / counter circuit with greatly reduced testing time for a circuit, thereby improving test efficiency and productivity. The timer / counter circuit includes a multiplexer for selecting one of a plurality of clocks according to a predetermined clock selection signal, ; A counter for counting in synchronization with a clock output from the multiplexer; And a multiplexer output selection unit for selecting a clock output from the multiplexer according to a predetermined selection signal and outputting the selected clock to a port unit. In the timer / counter circuit of the present invention configured as described above, a multiplexer output selection unit for selecting and outputting a clock output from the multiplexer according to a predetermined selection signal transfers the output to the test apparatus through the port unit, thereby testing a selection operation of the multiplexer There is an effect that can be performed in a short time.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제3도는 본 발명에 따른 타이머/카운터 회로의 구성도.FIG. 3 is a block diagram of a timer / counter circuit according to the present invention; FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960016450A KR100206906B1 (en) | 1996-05-16 | 1996-05-16 | Timer/counter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960016450A KR100206906B1 (en) | 1996-05-16 | 1996-05-16 | Timer/counter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970078023A true KR970078023A (en) | 1997-12-12 |
KR100206906B1 KR100206906B1 (en) | 1999-07-01 |
Family
ID=19458908
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960016450A KR100206906B1 (en) | 1996-05-16 | 1996-05-16 | Timer/counter circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100206906B1 (en) |
-
1996
- 1996-05-16 KR KR1019960016450A patent/KR100206906B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100206906B1 (en) | 1999-07-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050322 Year of fee payment: 7 |
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LAPS | Lapse due to unpaid annual fee |