KR970014421A - Reference Clock Supervisory Circuit - Google Patents

Reference Clock Supervisory Circuit Download PDF

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Publication number
KR970014421A
KR970014421A KR1019950024313A KR19950024313A KR970014421A KR 970014421 A KR970014421 A KR 970014421A KR 1019950024313 A KR1019950024313 A KR 1019950024313A KR 19950024313 A KR19950024313 A KR 19950024313A KR 970014421 A KR970014421 A KR 970014421A
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KR
South Korea
Prior art keywords
reference clock
signal
logical sum
output
signals
Prior art date
Application number
KR1019950024313A
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Korean (ko)
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KR100195008B1 (en
Inventor
이재곤
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950024313A priority Critical patent/KR100195008B1/en
Publication of KR970014421A publication Critical patent/KR970014421A/en
Application granted granted Critical
Publication of KR100195008B1 publication Critical patent/KR100195008B1/en

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Abstract

1. 청구범위에 기재된 발명이 속하는 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 기준 클럭 감시회로에 관한 것이다.The present invention relates to a reference clock monitoring circuit.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

본 발명의 목적은 기준 클럭의 하이상태 입력에 대한 오판을 제거하여 감시효율을 높일 수 있는 기준 클럭 감시회로를 제공함에 있다.An object of the present invention is to provide a reference clock monitoring circuit that can increase the monitoring efficiency by eliminating a mistake for the high state input of the reference clock.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 기준 클럭 감시회로에 있어서, 소정 샘플링클럭을 클럭입력단으로 입력받아 이에 동기하여 기준 클럭을 샘플링하여 쉬프트하여 그 샘플링상태신호를 출력하는 쉬프트 레지스터와, 상기 쉬프트 레지스터의 출력신호들을 입력받아 인접비트간의 출력신호를 배타적논리합연산하여 그 연산신호들을 출력하는 배타적 논리합연산수단과, 상기 배타적 논리합연산수단으로부터 연산신호들을 입력받아 논리합연산하여 그 논리합연산신호를 출력하는 논리합연산수단과, 기준 클럭 감시회로의 출력을 온 오프 스위칭하는 소정 인에이블신호와, 상기 논리합연산신호를 입력받으며, 상기 두 입력신호를 논리곱연산하여 그 논리곱연산신호를 출력하는 논리곱연산수단으로 구성한다.The present invention provides a reference clock monitoring circuit comprising: a shift register for inputting a predetermined sampling clock to a clock input stage, sampling and shifting a reference clock in synchronization with the clock signal, and outputting a sampling state signal; Exclusive logical summation means for performing exclusive logical sum operation of the output signal between bits and outputting the operation signals, logic summation means for receiving the operation signals from the exclusive logical summation operation and performing logical sum operation to output the logical sum operation signal, and reference clock monitoring And a logical enable operation unit for receiving a predetermined enable signal for switching the output of the circuit on and off, the logical sum operation signal, and for performing an AND operation on the two input signals and outputting the AND operation signal.

4. 발명의 중요한 용도4. Important uses of the invention

본 발명은 교환기등에서 중요히 사용될 수 있다.The present invention can be importantly used in an exchanger and the like.

Description

기준클럭 감시회로Reference Clock Supervisory Circuit

제2도는 본 발명의 바람직한 일 실시예에 따른 기준클럭 감시회로의 블럭구성도이다.2 is a block diagram of a reference clock monitoring circuit according to a preferred embodiment of the present invention.

Claims (3)

기준 클럭 감시회로에 있어서: 서정 샘플링클럭을 클럭입력단으로 입력받아 이에 동기하여 기준 클럭을 샘플링하여 쉬프트하여 그 샘플링상태신호를 출력하는 쉬프트 레지스터와; 상기 쉬프트 레지스터의 출력신호들을 입력받아 인접비트간의 출력신호를 배타적논리합연산하여 그 연산신호들을 출력하는 배타적 논리합연산수단과; 상기 배타적 논리연합산수단으로부터 연산신호들을 입력받아 논리합연산하여 그 논리합연산신호를 출력하는 논리합연산수산과; 기준 클럭 감시회로의 출력을 온 오프 스위칭하는 소정 인에이블신호와, 상기 논리합연산신호를 입력받으며, 상기 두 입력신호를 논리곱연산하여 그 논리곱연산신호를 출력하는 논리곱연산수산으로 구성함을 특징으로하는 기준 클럭 감시회로.A reference clock monitoring circuit, comprising: a shift register for receiving a lyric sampling clock as a clock input terminal, synchronously sampling and shifting a reference clock to output a sampling state signal; Exclusive logical summating means for receiving the output signals of the shift register and performing an exclusive logical sum operation on the output signals between adjacent bits and outputting the operation signals; A logical sum arithmetic operation for receiving the arithmetic signals from the exclusive logic arithmetic means and performing a logical sum operation to output the logical sum operation signal; And a predetermined enable signal for switching the output of the reference clock supervisor circuit on and off, and the logical sum operation signal, and receiving the logical sum operation of the two input signals and outputting the logical product operation signal. A reference clock supervisory circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950024313A 1995-08-07 1995-08-07 Reference Clock Supervisory Circuit KR100195008B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950024313A KR100195008B1 (en) 1995-08-07 1995-08-07 Reference Clock Supervisory Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950024313A KR100195008B1 (en) 1995-08-07 1995-08-07 Reference Clock Supervisory Circuit

Publications (2)

Publication Number Publication Date
KR970014421A true KR970014421A (en) 1997-03-29
KR100195008B1 KR100195008B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950024313A KR100195008B1 (en) 1995-08-07 1995-08-07 Reference Clock Supervisory Circuit

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KR (1) KR100195008B1 (en)

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Publication number Publication date
KR100195008B1 (en) 1999-06-15

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