KR970077503A - Method of forming device isolation region in semiconductor device - Google Patents

Method of forming device isolation region in semiconductor device Download PDF

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Publication number
KR970077503A
KR970077503A KR1019960018910A KR19960018910A KR970077503A KR 970077503 A KR970077503 A KR 970077503A KR 1019960018910 A KR1019960018910 A KR 1019960018910A KR 19960018910 A KR19960018910 A KR 19960018910A KR 970077503 A KR970077503 A KR 970077503A
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KR
South Korea
Prior art keywords
side wall
forming
semiconductor substrate
oxide film
isolation region
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Application number
KR1019960018910A
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Korean (ko)
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KR100202177B1 (en
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손정환
정재홍
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문정환
Lg 반도체 주식회사
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Priority to KR1019960018910A priority Critical patent/KR100202177B1/en
Publication of KR970077503A publication Critical patent/KR970077503A/en
Application granted granted Critical
Publication of KR100202177B1 publication Critical patent/KR100202177B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체장치의 소자분리영역 형성방법에 관한 것으로서, 반도체기판상에 패드산화막과 질화막을 형성하고 소정 부분을 제거하여 필드부분을 한정하는 공정과, 상기 패드산화막과 질화막의 측면에 제1측벽을 형성하고, 이 제1측벽의 측면에 제2측벽을 형성하는 공정과, 상기 제1측벽과 제2측벽을 마스크로하여 반도체기판의 상기 필드부분을 소정 깊이로 식각하여 홈을 형성하고 상기 제2측벽을 제거하는 공정과, 상기 홈과 상기 제2측벽이 제거되어 노출된 부분의 반도체기판을 산화하여 소자분리 영역을 형성하는 공정과, 상기 질화막, 패드산화막 및 제1측벽 제거하여 반도체기판의 활성영역을 노출시키는 공정을 구비한다. 따라서, 활성영역의 면적이 축소되는 것을 방지할 수 있으며, 또한, 소자분리영역과 활성영역의 계면에 스트레스를 완화시킬 수 있다.The present invention relates to a method for forming a device isolation region of a semiconductor device, comprising: forming a pad oxide film and a nitride film on a semiconductor substrate and removing a predetermined portion to define a field portion; and a first side wall on the side of the pad oxide film and the nitride film. Forming a second side wall on the side of the first side wall, and etching the field portion of the semiconductor substrate to a predetermined depth using the first side wall and the second side wall as a mask to form a groove; Removing the second side wall, oxidizing the semiconductor substrate of the exposed portion by removing the groove and the second side wall to form an isolation region, and removing the nitride film, the pad oxide film, and the first side wall to remove the semiconductor substrate. Exposing the active region. Therefore, the area of the active region can be prevented from being reduced, and stress at the interface between the device isolation region and the active region can be alleviated.

Description

반도체장치의 소자분리영역 형성방법Method of forming device isolation region in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(A) 내지 (D)는 본 발명에 따른 반도체장치의 소자분리영역 형성방법을 도시하는 공정도.2A to 2D are process drawings showing a method for forming an isolation region in a semiconductor device according to the present invention.

Claims (4)

반도체기판상에 패드산화막과 질화막을 형성하고 소정 부분을 제거하여 필드부분을 한정하는 공정과, 상기 패드산화막과 질화막의 측면에 제1측벽을 형성하고, 이 제1측벽의 측면에 제2측벽을 형성하는 공정과, 상기 제1측벽과 제2측벽을 마스크로하여 반도체기판의 상기 필드부분을 소정 깊이로 식각하여 홈을 형성하고, 상기 제2측벽을 제거하는 공정과, 상기 홈과 상기 제2측벽이 제거되어 노출된 부분의 반도체기판을 산화하여 소자분리영역을 한정하는 공정과, 상기 질화막, 패드산화막 및 제1측벽 제거하여 반도체기판의 활성 영역을 노출시키는 공정을 구비하는 반도체장치의 소자분리영역 형성방법.Forming a pad oxide film and a nitride film on the semiconductor substrate and removing a predetermined portion to define a field portion; forming a first side wall on the side surfaces of the pad oxide film and the nitride film, and forming a second side wall on the side surfaces of the first side wall. Forming a groove by etching the field portion of the semiconductor substrate to a predetermined depth using the first side wall and the second side wall as a mask, and removing the second side wall; Oxidizing the semiconductor substrate of the exposed portion by removing sidewalls to define an isolation region, and removing the nitride film, the pad oxide film, and the first sidewall to expose the active region of the semiconductor substrate. Zone Formation Method. 제1항에 있어서, 상기 제2측벽은 산화막 또는 다결정실리콘으로 형성하는 반도체장치의 소자분리영역 형성방법.The method of claim 1, wherein the second side wall is formed of an oxide film or polycrystalline silicon. 제2항에 있어서, 상기 제2측벽은 200∼1000A의 두께로 형성하는 반도체장치의 소자분리영역 형성방법.The method of claim 2, wherein the second side wall is formed to a thickness of 200 to 1000 A. 4. 제1항에 있어서, 상기 홈을 500∼3000A의 깊이로 이방성 식각하는 반도체장치의 소자분리영역 형성방법.The method of claim 1, wherein the groove is anisotropically etched to a depth of 500 to 3000 A. 5. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018910A 1996-05-31 1996-05-31 Method of forming an element isolation region in a semiconductor device KR100202177B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018910A KR100202177B1 (en) 1996-05-31 1996-05-31 Method of forming an element isolation region in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018910A KR100202177B1 (en) 1996-05-31 1996-05-31 Method of forming an element isolation region in a semiconductor device

Publications (2)

Publication Number Publication Date
KR970077503A true KR970077503A (en) 1997-12-12
KR100202177B1 KR100202177B1 (en) 1999-06-15

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KR100202177B1 (en) 1999-06-15

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