KR930011209A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR930011209A
KR930011209A KR1019910019891A KR910019891A KR930011209A KR 930011209 A KR930011209 A KR 930011209A KR 1019910019891 A KR1019910019891 A KR 1019910019891A KR 910019891 A KR910019891 A KR 910019891A KR 930011209 A KR930011209 A KR 930011209A
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KR
South Korea
Prior art keywords
polysilicon
oxide film
cvd oxide
trench
forming
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Application number
KR1019910019891A
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Korean (ko)
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KR940009354B1 (en
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김용배
김병렬
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019910019891A priority Critical patent/KR940009354B1/en
Publication of KR930011209A publication Critical patent/KR930011209A/en
Application granted granted Critical
Publication of KR940009354B1 publication Critical patent/KR940009354B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

폴리실리콘을 채우기 전 CVD 산화막을 집적한 후 폴리실리콘을 채운 후 CVD 산화막을 전부 에치백함으로써 채워진 폴리실리콘과 트랜치 윗벽 사이에 약간 틈이 벌어지게 하여 폴리실리콘이 산화될 때 부피 팽창으로 인한 스트레스를 감소시켜 주며 또한 CVD 애치백시 이전에 있던 트랜치 마스크 막으로 사용한 CVD 산화막까지 에치백하고 폴리실리콘을 산화하기 때문에, 종래의 방식에서 폴리산화를 하고 CVD 산화막을 식각할 때 문제가 트렌치 분리 부분 윗부분의 산화막이 모두 제거되는 문제가 해결된다.Integrate the CVD oxide film before filling the polysilicon and then fill the polysilicon and then etch back all the CVD oxide so that there is a slight gap between the filled polysilicon and the trench top wall to reduce the stress due to volume expansion when the polysilicon is oxidized Since it etches back to the CVD oxide film used as the trench mask film before CVD ashback and oxidizes the polysilicon, the problem of poly-oxidation and etching the CVD oxide film in the conventional method is a problem of oxide film on the trench isolation part. This eliminates the problem.

Description

반도체 장치의 소자 분리 방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따르는 반도체 장치의 소자 분리 방법을 나타낸 도면.2 is a view showing a device isolation method of a semiconductor device according to the present invention.

Claims (5)

반도체 기판 상에 제1산화막, 질화막, 제CVD 산화막을 형성하고 개구부를 형성하는 공정, 개구부 측벽에 스페이서를 형성하고 트렌치 식각을 행하는 공정, 트랜치 측벽에 산화막을 형성하고 채널 저지 이온 주입을 행하는 공정으로 웨이퍼를 준비하는 공정에 있어서, 제2CVD 산화막을 전면에 형성하고 폴리실리콘을 트렌치 내부에 형성하는 공정, 질화막 윗부분의 CVD 산화막을 제거하는 공정, 트렌치 내부의 폴리실리콘의 일부를 산화하는 공정, 질화막, 제1산화막을 차례로 제거하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.Forming a first oxide film, a nitride film, and a CVD oxide film on a semiconductor substrate, forming an opening, forming a spacer on the sidewall of the opening and etching the trench; forming an oxide film on the sidewall of the trench, and implanting channel blocking ions. In the process of preparing a wafer, a process of forming a second CVD oxide film on the entire surface and forming polysilicon inside the trench, removing a CVD oxide film on the upper part of the nitride film, oxidizing a part of the polysilicon inside the trench, a nitride film, And a step of sequentially removing the first oxide film. 제1항에 있어서, 폴리실리콘은 불순물이 침적되지 않거나(undoped) 또는 침적된(doped)폴리실리콘 임을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1 wherein the polysilicon is polysilicon that is undoped or doped with impurities. 제1항에 있어서, 질화막 윗부분의 CVD산화막을 제거할때 폴리실리콘과 트렌치 측벽 윗부분에 틈이 생기게하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1, wherein a gap is formed in the polysilicon and the trench sidewalls when the CVD oxide film is removed from the nitride film. 제1항에 있어서, 질화막 윗부분의 CVD 산화막을 제거할 때 제1CVD 산화막과 제2CVD 산화막을 동시에 건식 식각 방식으로 식각하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1, wherein the first CVD oxide and the second CVD oxide are simultaneously etched by dry etching when the CVD oxide over the nitride film is removed. 제1항에 있어서, 개구부가 1.0㎛ 이하의 소자 분리 영역이 됨을 특징으로 하는 반도체 장치의 소자 분리방법.The device isolation method according to claim 1, wherein the opening is an element isolation region of 1.0 m or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910019891A 1991-11-09 1991-11-09 Method of isolating device of semiconductor device KR940009354B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019891A KR940009354B1 (en) 1991-11-09 1991-11-09 Method of isolating device of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019891A KR940009354B1 (en) 1991-11-09 1991-11-09 Method of isolating device of semiconductor device

Publications (2)

Publication Number Publication Date
KR930011209A true KR930011209A (en) 1993-06-24
KR940009354B1 KR940009354B1 (en) 1994-10-07

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KR1019910019891A KR940009354B1 (en) 1991-11-09 1991-11-09 Method of isolating device of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849079B1 (en) * 2002-06-28 2008-07-30 매그나칩 반도체 유한회사 Method for element isolating of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849079B1 (en) * 2002-06-28 2008-07-30 매그나칩 반도체 유한회사 Method for element isolating of semiconductor device

Also Published As

Publication number Publication date
KR940009354B1 (en) 1994-10-07

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