KR970076316A

KR970076316A - Multiplier for Neural Networks and Multiplication Method

Info

Publication number: KR970076316A
Application number: KR1019960014845A
Authority: KR
Inventors: 김종문; 송윤선
Original assignee: 양숭택; 한국전자통신연구원
Priority date: 1996-05-07
Filing date: 1996-05-07
Publication date: 1997-12-12
Also published as: KR0162770B1

Abstract

본 발명은 신경 회로망에 사용되는 곱셈기 및 그 곱셈방법에 관한 것으로서, 그 특징은 디지털 신경 회로망을 위한 소정의 비트수(N)×소정의 비트수(N)의 곱셈방법에 있어서, 곱셈 결과로 나오는 2N개의 중에서 최하위 비트(비트 0)부터 상위 비트 순으로 차례로 N-1개의 비트(비트 N-2, 비트 N-3, …, 비트 1 및 비트 0)와 최상위에서 두번째 비트(비트 2N-1)를 버리는 제1과정 및 상기 제1과정의 결과로 남은 나머지 N개의 비트(비트 2N, 비트 2N-2, 비트 2N-3, 비트 2N-4, …, 비트 N+1, 비트 N 및 비트 N-1)를 곱셈 결과로 선택하는 제2과정으로 이루어지는 데에 있으므로, 상술한 바와 같은 본 발명은 종래의 신경망을 위한 곱셈기에 비해 더 우수한 인식률을 나타내는 데에 그 효과가 있다.The present invention relates to a multiplier used in a neural network and a multiplication method thereof, characterized in that in a multiplication method of a predetermined number of bits (N) × a predetermined number of bits (N) for a digital neural network, (Bits N-2, N-3, ..., bit 1 and bit 0) and the second bit (bit 2N-1) from the lowest bit (bit 0) Bit 2N-3, bit 2N-4, ..., bit N + 1, bit N and bit N-1 remaining as a result of the first process and the remaining N bits 1) as a result of the multiplication. Therefore, the present invention as described above is effective in showing a better recognition rate as compared with the multiplier for the conventional neural network.

Description

Multiplier for Neural Networks and Multiplication Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 신경망을 위한 곱셈기의 전체 구성도, 제2도는 본 발명에 따른 신경망을 위한 곱셈기에 사용되는 종래의 2의 보수 병렬 곱셈기의 구조도.FIG. 2 is a schematic diagram of a conventional two's complement parallel multiplier used in a multiplier for a neural network according to the present invention; FIG. 2 is a block diagram of a multiplier for a neural network according to the present invention;

Claims

In a multiplication method of a predetermined number of bits (N) for a digital neural network multiplied by a predetermined number of bits (N), the multiplication result is multiplied by N-1 in order from the least significant bit (bit 0) A first step of discarding bits (bits N-2, N-3, ..., bit 1 and bit 0) and a second bit (bit 2N-1) And the remaining N bits (bit 2N, bit 2N-2, bit 2N-3, bit 2N-4, ..., bit N + 1, bit N and bit N-1) remaining as a result of the first process And a second step of selecting a multiplication factor for the neural network.

The method of claim 1, wherein the predetermined number of bits (N) is 4 bits; A first step of discarding three bits (bit 2, bit 1 and bit 0) and a second bit (bit 6) from the most significant bit (bit 0) to the most significant bit among the eight bits resulting from the multiplication; And a second step of selecting the remaining four bits (bit 7, bit 5, bit 4 and bit 3) remaining as a result of the first process as a result of the multiplication.

A multiplier having a predetermined number of bits (N) for a digital neural network multiplied by a predetermined number of bits (N), the multiplier having a predetermined number of bits (N) Multiplying means for performing a multiplication of a predetermined number of bits (N) to output a result value of 2N bits; And a multiplier for multiplying a result value of the 2N bits of the multiplication means and two input values of N bits and outputting N-1 bits (1) in order from the least significant bit (bit 0) (The bit 2N, the bit 2N-2, the bit 2N-3) of the remaining N bits (bit N-2, bit N-3, ..., bit 1 and bit 0) , The bit 2N-4, ..., the bit N + 1, the bit N and the bit N-1) as the multiplication result of the multiplier and outputting the result of the multiplication with N bits. Multiplier for.

4. The method of claim 3, wherein the predetermined number of bits (N) is 4 bits; A multiplication means for receiving two input values of four bits and performing a multiplication of four bits by four bits to output a result value of eight bits; And a multiplier for multiplying the result value of the multiplication means by the 8-bit result value and the 2 input values of 4 bits and receiving 3 bits (bit 2 (Bit 7, bit 5, bit 4, and bit 3) as a result of the multiplication of the multiplier, and outputs the remaining four bits And a maximum value correcting means for outputting a multiplication result.

※ Note: It is disclosed by the contents of the first application.