KR970076283A

KR970076283A - Unidirectional Serial Data Transmission Device

Info

Publication number: KR970076283A
Application number: KR1019960019356A
Authority: KR
Inventors: 도영칠
Original assignee: 유상부; 삼성중공업 주식회사
Priority date: 1996-05-31
Filing date: 1996-05-31
Publication date: 1997-12-12

Abstract

본 발명은 단일방향 직렬데이터 전송장치에 관한 것으로, 병직렬변환기, 직병렬변환기, 카운터 등을 구비하여 송신측 시스템과 수신측 시스템간에 직렬데이터를 8비트씩 전송하는 경우 병렬데이타를 전송하는 경우에 비하여 적은 전송회선을 사용할 수 있는 효과가 있다.The present invention relates to a unidirectional serial data transmission apparatus, comprising a parallel-to-parallel converter, a serial-to-parallel converter, a counter, and the like, in case of transmitting 8-bit serial data between a transmitting system and a receiving system. Compared with this, there is an effect that fewer transmission lines can be used.

Description

Unidirectional Serial Data Transmission Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 단일방향 직렬데이터 전송장치를 나타내는 구성도.1 is a block diagram showing a unidirectional serial data transmission apparatus according to the present invention.

Claims

A device for transmitting data in a single direction between a first microcomputer on a transmitting side and a second microcom on a receiving side connected in circuit, converting 8-bit parallel data supplied through a first data bus into serial data and receiving the data. A transmitter for transmitting the converted serial data to the receiving side in association with the processing status of the receiving side; And a receiving unit converting serial data supplied from the transmitting unit into parallel data in an 8-bit processing unit and outputting the parallel data to a second data bus.

The parallel serial system of claim 1, wherein the transmitting unit stores parallel data carried on a data bus on the transmission side according to a write control signal generated by the first microcomputer, and outputs the stored data in series according to a predetermined first clock. A converter; A clock generator which generates a second clock synchronized with a reference clock which is a reference for data transmission from the regular write control signal; A counter for generating a gate pulse signal for transmitting data from the reference clock and inverting the gate pulse when the count value of the reference clock reaches a set value; And a first D flip-flop for receiving a termination signal from a receiving side and generating a first data request signal for informing an output request to a microcomputer of the transmitter.

2. The apparatus of claim 1, wherein the receiver comprises: a second D flip-flop for generating a second data request signal and an end signal for informing an output request from the gate pulse to a receiving side microcomputer; The serial data supplied according to the serial transmission clock transmitted from the transmitter is stored, and the data stored in accordance with the read control signal humanized from the receiving microcomputer in response to the second data request signal are paralleled to the data bus of the receiving side. A unidirectional serial data transmission device comprising a serial-to-parallel converter for outputting.

※ Note: The disclosure is based on the initial application.