KR970076157A - How to control the GPIO board - Google Patents
How to control the GPIO board Download PDFInfo
- Publication number
- KR970076157A KR970076157A KR1019960015359A KR19960015359A KR970076157A KR 970076157 A KR970076157 A KR 970076157A KR 1019960015359 A KR1019960015359 A KR 1019960015359A KR 19960015359 A KR19960015359 A KR 19960015359A KR 970076157 A KR970076157 A KR 970076157A
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- South Korea
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- port
- input
- output
- ports
- gpio
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Abstract
본 발명은 GPIO보드에서 입/출력되는 데이터에 대한 입/출력포트의 지정과 그 포트에 공급되는 내부클럭 또는 외부클럭의 발생여부를 제어하기 위한 GPIO보드의 포트제어방법을 제공한다.The present invention provides a GPIO board port control method for controlling the designation of input / output ports for data input / output from a GPIO board and the generation of an internal clock or an external clock supplied to the port.
그에 따라 본 발명은 메인프로세서(2)와 PCI로컬버스(6)와의 데이터인터페이스동작을 위한 복수의 입력포트와 복수의 출력포트를 갖춘 GPIO보드(4)에 있어서; 상기 GPIO보드(4)의 데이터레지스터내용에서 복수의 입력포트와 복수의 출력포트에 대한 포트인에이블 지정과 그 인에이블지정된 입력포트와 출력포트에 공급되는 동기클럭에 대해 외부클럭을 발생시킬 것인지와 내부클럭을 발생시킬 것인지를 지정하는 단계로 이루어진 것을 특징으로 한다.Accordingly, the present invention provides a GPIO board (4) having a plurality of input ports and a plurality of output ports for data interface operation between a main processor (2) and a PCI local bus (6); Whether to generate an external clock for a port enable designation for a plurality of input ports and a plurality of output ports in the data register contents of the GPIO board 4 and a synchronous clock supplied to the input port and the output port designated to be enabled, And designating whether to generate an internal clock.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 본 발명의 방법이 적용된 GPIO보드와 메인프로세서와의 데이터 입/출력구조를 나타낸 도면.FIG. 1 is a diagram showing a data input / output structure between a GPIO board and a main processor to which the method of the present invention is applied; FIG.
제2도 (A)는 제1도에 도시된 인터럽트인식레지스터의 인터럽트가 발생된 포트의 확인을 위한 레지스터 상태를 나타낸 도면.FIG. 2 (A) shows a register state for confirming an interrupt-generated port of the interrupt recognition register shown in FIG. 1; FIG.
제2도 (B)는 제1도에 도시된 콘트롤레지스터의 GPIO보드의 동작을 제어하기 위한 레지스터의 상태를 나타낸 도면.Fig. 2 (B) shows the state of the register for controlling the operation of the GPIO board of the control register shown in Fig. 1; Fig.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960015359A KR970076157A (en) | 1996-05-10 | 1996-05-10 | How to control the GPIO board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960015359A KR970076157A (en) | 1996-05-10 | 1996-05-10 | How to control the GPIO board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970076157A true KR970076157A (en) | 1997-12-12 |
Family
ID=66219439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960015359A KR970076157A (en) | 1996-05-10 | 1996-05-10 | How to control the GPIO board |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970076157A (en) |
-
1996
- 1996-05-10 KR KR1019960015359A patent/KR970076157A/en not_active Application Discontinuation
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| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |