KR970057706A - Pattern Display Method and Circuit of TV Receiver - Google Patents

Pattern Display Method and Circuit of TV Receiver Download PDF

Info

Publication number
KR970057706A
KR970057706A KR1019950056561A KR19950056561A KR970057706A KR 970057706 A KR970057706 A KR 970057706A KR 1019950056561 A KR1019950056561 A KR 1019950056561A KR 19950056561 A KR19950056561 A KR 19950056561A KR 970057706 A KR970057706 A KR 970057706A
Authority
KR
South Korea
Prior art keywords
pattern
address
signal
television receiver
video ram
Prior art date
Application number
KR1019950056561A
Other languages
Korean (ko)
Other versions
KR100189528B1 (en
Inventor
안덕용
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950056561A priority Critical patent/KR100189528B1/en
Publication of KR970057706A publication Critical patent/KR970057706A/en
Application granted granted Critical
Publication of KR100189528B1 publication Critical patent/KR100189528B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/16—Picture reproducers using cathode ray tubes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/66—Circuits for processing colour signals for synchronous demodulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/67—Circuits for processing colour signals for matrixing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
    • H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Abstract

텔레비전 영상신호를 색복조하고 A/D 하여 먹싱한 후 비디오램에 기록하는 텔레비전수상기의 패턴표시방법에 있어서,상기 합성영상신호의 HV동기를 카운터하여 메모리라이트 어드레스를 발생하고,1H 패턴신호를 검출하여 패턴위치를 검출하여,상기 패턴에 대응하는 위치에 해당로우어드레스로 고정시켜 선택에 의해 동일 데이타를 반복리드하여 패턴을 표시토록 구성됨.A pattern display method of a television receiver, which color-decodes a television video signal, performs A / D, muxes it, and writes it to a video RAM, wherein the HV synchronization of the composite video signal is countered to generate a memory write address, and to detect a 1H pattern signal. By detecting the pattern position, fixing it with the corresponding low address at the position corresponding to the pattern, and repeatedly reading the same data by selection to display the pattern.

Description

텔레비전 수상기의 패턴표시방법 및 회로Pattern Display Method and Circuit of Television Receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 회로도,1 is a circuit diagram according to the present invention,

제2도는 본 발명에 따른 위치 검출 파형도,2 is a position detection waveform diagram according to the present invention;

제3도는 본 발명에 따른 메모리 맵도.3 is a memory map diagram according to the present invention.

Claims (5)

텔레비전 영상신호를 색복조하고 A/D하여 먹싱한후 비디오램에 기록하는 텔레비전수상기의 패턴표시회로에 있어서,상기 합성영상신호의 HV동기를 카운트하여 메모리라이트 어드레스를 발생하는 제1수단과,1H 패턴신호를 검출하는 위치검출수단과, 해당로우어드레스를 고정하는 메모리 리드어드레스 발생수단과, 상기 동작을 선택하는 선택수단으로 구성됨을 특징으로 하는 텔레비전수상기의 패턴표시회로.A pattern display circuit of a television receiver which color-decodes a television video signal, performs A / D, muxes it, and writes it to a video RAM, comprising: first means for counting HV synchronization of the composite video signal to generate a memory write address; A pattern display circuit of a television receiver comprising: position detecting means for detecting a pattern signal, memory lead address generating means for fixing a corresponding low address, and selecting means for selecting the operation. 텔레비전 영상신호를 색복조하고 A/D하여 먹싱한후 비디오램에 기록하는 텔레비전수상기의 패턴표시방법에 있어서,상기 합성영상신호의 HV동기를 카운트하여 메모리라이트어드레스를 발생하고,1H패턴신호를 검출하여 패턴위치를 검출하며, 상기 패턴에 대응하는 위치에 해당로우어드레스로 고정시켜 선택에 의해 동기 데이타를 반복리드하여 패턴을 표시토록 구성됨을 특징으로 하는 텔레비전수상기의 패턴표시방법.A pattern display method of a television receiver for color demodulation, A / D, muxing, and recording of a television video signal, wherein the HV synchronization of the composite video signal is counted to generate a memory light address, and a 1H pattern signal is detected. And detecting a pattern position, and fixing a low address at a position corresponding to the pattern so as to repeatedly read synchronous data by selection so that the pattern is displayed. 텔레비전 영상신호를 색복조하고 A/D하여 먹싱한후 비디오램에 기록하는 텔레비젼수상기의 패턴표시회로에 있어서,상기 텔레비전수상가의 합성 영상신호(VS)을, Y, R-Y, B-Y 및 H, V-SYNC로 분리하여 출력하는 색복조 및 동기분리부(100)와, 상기 분리된 Y, R-Y, B-Y 신호를 디지탈 신호로 변환하는 3채널 A/D 변환기(102)와,상기 3채널 D/A변환기(102) 출력 3개의 신호를 다중화하는 멀티플랙서(104)와,상기 멀티플렉서(104)에서 다중화된 영상신호를 저장하는 비디오램(108)과,상기 비디오램(108)의 억세스를 제어하는 콘트롤러(106)으로 구성되며,상기 비디오램(108)에서 리드된 출력을 디믹싱하는 Y/C 디멀티플렉서(110)와,상기 Y/C디멀티플렉서(110)의 출력을 아날로그 신호로 변환하는 D/A변환기(112)와,상기 아날로그화된 Y/C신호를 R,G,B 신호를 변환하여 CTR(116)에 제공하여 표시토록 하는 메트릭스회로(114)로 구성됨을 특징으로 하는 텔레비전수상기의 패턴표시회로.In a pattern display circuit of a television receiver for color demodulating, A / Ding, muxing a television video signal, and recording the same on a video RAM, the composite video signal VS of the television receiver is Y, RY, BY, H, V. A color demodulation and synchronization unit 100 for separating and outputting by SYNC, a three-channel A / D converter 102 for converting the separated Y, RY, and BY signals into a digital signal, and the three-channel D / A A multiplexer 104 for multiplexing the three signals outputted from the converter 102, a video RAM 108 for storing the video signal multiplexed by the multiplexer 104, and a control for accessing the video RAM 108. A controller 106, Y / C demultiplexer 110 for demixing the output read from the video RAM 108, and D / A for converting the output of the Y / C demultiplexer 110 into an analog signal Converter 112 and the analogized Y / C signal is converted to R, G, B signal and provided to the CTR (116) Characterized in that a lock consisting of a matrix circuit 114 for television receiver display circuit pattern. 제3항에 있어서,상기 색복조 및 동기분리부(100)에서 동기 분리된 H-SYNC로부터 시스템클럭(fs)을 발행하는 PLL부(118)와,상기 PLL부(118)에서 록킹된 H-SYNC와 동기분리 출력 V-SYNC로 상기 비디오램(108)의 라이트 어드레스를 제어하는 메모리 라이트 어드레스 발생기(120)와,상기 비디오램(108)의 리드 어드레스를 제어하는 메모리 리드 어드레스발생기(122)를 더추가함을 특징으로 하는 텔레비전수상기의 패턴표시회로.According to claim 3, PLL unit 118 for issuing a system clock (fs) from the H-SYNC synchronously separated in the color demodulation and synchronization separation unit 100, H- locked in the PLL unit 118 A memory write address generator 120 controlling a write address of the video RAM 108 and a memory read address generator 122 controlling a read address of the video RAM 108 using SYNC and a synchronously separated output V-SYNC. The pattern display circuit of the television receiver further comprising. 제3항에 있어서,상기 메모리 리드 어드레스발생기(122)는 그 내부에 V,H-SYNC 로 수평위치를 검출하는 카운터와,상기 메모리에서 리드어드레스의 로우 어드레스를 일정번지로 고정하는 로우 어드레스 고정부로 구성됨을 특징으로 하는 텔레비전 수상기의 패턴표시회로.According to claim 3, The memory read address generator 122 is a counter for detecting the horizontal position in the V, H-SYNC therein, and a row address fixing unit for fixing the row address of the lead address in the memory to a predetermined address Pattern display circuit of a television receiver, characterized in that consisting of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950056561A 1995-12-26 1995-12-26 A pattern display circuit of television receiver KR100189528B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950056561A KR100189528B1 (en) 1995-12-26 1995-12-26 A pattern display circuit of television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950056561A KR100189528B1 (en) 1995-12-26 1995-12-26 A pattern display circuit of television receiver

Publications (2)

Publication Number Publication Date
KR970057706A true KR970057706A (en) 1997-07-31
KR100189528B1 KR100189528B1 (en) 1999-06-01

Family

ID=19444422

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950056561A KR100189528B1 (en) 1995-12-26 1995-12-26 A pattern display circuit of television receiver

Country Status (1)

Country Link
KR (1) KR100189528B1 (en)

Also Published As

Publication number Publication date
KR100189528B1 (en) 1999-06-01

Similar Documents

Publication Publication Date Title
JPH04137886A (en) 4-screen split display device
KR880014478A (en) Computer video demultiplexer
US5408474A (en) Apparatus for multiplexing digital video and a digital sub-signal and method thereof
KR970057706A (en) Pattern Display Method and Circuit of TV Receiver
JPH0617370Y2 (en) Digital VCR sync signal sharing circuit
JP2593721Y2 (en) Screen superimposition circuit
KR970004742A (en) Image display device
JP2000013784A (en) Multidisplay monitoring system
JPS61172484A (en) Video field decoder
KR900002635A (en) Multi Screen Generation Circuit
US5282035A (en) 1-Field memory synchronizer and synchronizing method
KR100233520B1 (en) Visitor watching system in absence
JPS6284678A (en) Television receiver
KR0168999B1 (en) Video cassette recorder
KR0133459B1 (en) Aspect change circuit of tv
JPH0833716B2 (en) Video signal converter
KR100230299B1 (en) Multiple closed circuit television
KR970004746A (en) Plasma Display Panel TV Frame Memory Device
KR960030671A (en) Image processing device with multi-screen display function
JPH05127645A (en) Display device
KR970022714A (en) Computer and TV, video signal interface device
KR100234259B1 (en) Aspect ratio conversion circuit in the video display device
JPS6397982U (en)
JPH0583618A (en) Synchronous coupling method for television camera system
KR970024913A (en) Video signal converter for video shooting

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061227

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee