KR970055555A - Clock Generation Circuit of Digital Phase-locked Loop (D-PLL) - Google Patents

Clock Generation Circuit of Digital Phase-locked Loop (D-PLL) Download PDF

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Publication number
KR970055555A
KR970055555A KR1019950053366A KR19950053366A KR970055555A KR 970055555 A KR970055555 A KR 970055555A KR 1019950053366 A KR1019950053366 A KR 1019950053366A KR 19950053366 A KR19950053366 A KR 19950053366A KR 970055555 A KR970055555 A KR 970055555A
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KR
South Korea
Prior art keywords
clock
locked loop
digital phase
generation circuit
jitter
Prior art date
Application number
KR1019950053366A
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Korean (ko)
Other versions
KR100238747B1 (en
Inventor
최재일
Original Assignee
정장호
Lg 정보통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정장호, Lg 정보통신 주식회사 filed Critical 정장호
Priority to KR1019950053366A priority Critical patent/KR100238747B1/en
Publication of KR970055555A publication Critical patent/KR970055555A/en
Application granted granted Critical
Publication of KR100238747B1 publication Critical patent/KR100238747B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 디지탈 전압 제어발진기(VCD) 구현시 클럭제거를 할 때 지터(JITTER)를 최소화시키도록 한 디지탈 위상 동기루프의 클럭발생회로에 관한 것이다.The present invention relates to a clock generation circuit of a digital phase locked loop that minimizes jitter when removing a clock when implementing a digital voltage controlled oscillator (VCD).

종래 기술은 클럭 감소시 클럭 1개 만큼의 클럭폭이 빠지게 되어 클럭혼들림 현상인 지터(JITTER)가 커져 출력 파형의 불안정을 초래하는 문제점이 있었다.In the prior art, when the clock is decreased, the clock width of one clock is lost, which causes jitter (JITTER), which is a clock congestion phenomenon, to increase the output waveform.

이를 개선코자하여 본 발명은 반폭 클럭제거와 180°위상변이를 이용하여 1개의 클럭을 제거하고 2분주된 클럭을 이용하여 익스클루시브 어어게이트에 의해 원래의 클럭을 복원함으로써 지터현상을 최소화하여 회로동작의 안정화를 도모코자 한 것이다.To improve this, the present invention minimizes jitter by eliminating one clock by using half-width clock removal and 180 ° phase shift, and restoring the original clock by an exclusive aggregator using a two-division clock. This is to stabilize the operation.

Description

디지탈 위상동기루프(D-PLL)의 클럭발생회로Clock Generation Circuit of Digital Phase-locked Loop (D-PLL)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 클럭발생회로 구성도.3 is a block diagram of a clock generation circuit according to the present invention.

Claims (2)

기본클럭(INCLK)과 클럭감쇠신호(DISCLK)를 입력받아 2분주하는 2분주회로(10)와 상기 2분주회로(10)의 출력을 입력받아 원래의 클럭을 생성하는 익스클루시브 오어게이트(EX1)로 구성된 것을 특징으로 하는 디지탈 위상동기루프(D-pu)의 클럭발생회로.Exclusive or gate (EX) that receives the basic clock (INCLK) and the clock attenuation signal (DISCLK) and divides the signal into two divided circuits 10 and the output of the divided circuit 10 to generate an original clock. 1 ) A clock generation circuit of a digital phase locked loop (D-pu), characterized in that consisting of. 제1항에 있어서 상기 2분주회로(10)는 기본클럭(INCLK)을 입력받아 2분주된 신호를 출력하는 제1디플립플롭(FF1)과 클러감쇠신호(DISCLK)와 기본클럭(INCLK)을 인버터(IN1)를 통해 반전시킨 클럭을 입력받아 클럭의 하강에지에서 2분주 카운트 동작되도록 하는 제2디플립플롭(FF2)으로 구성된 것을 특징으로 하는 디지탈 위상동기루프(D-pu)의 클럭발생회로.The second divider circuit 10 receives the basic clock INCLK and outputs a first divided flip-flop FF 1 , a clock attenuation signal DISCLK, and a basic clock INCLK. The clock of the digital phase-locked loop (D-pu), characterized in that consisting of a second flip-flop (FF2) for receiving a clock inverted through the inverter IN 1 to operate a two-division count at the falling edge of the clock Generating circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053366A 1995-12-21 1995-12-21 Clock generating circuit of digital phase locked loop KR100238747B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053366A KR100238747B1 (en) 1995-12-21 1995-12-21 Clock generating circuit of digital phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053366A KR100238747B1 (en) 1995-12-21 1995-12-21 Clock generating circuit of digital phase locked loop

Publications (2)

Publication Number Publication Date
KR970055555A true KR970055555A (en) 1997-07-31
KR100238747B1 KR100238747B1 (en) 2000-01-15

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ID=19442313

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950053366A KR100238747B1 (en) 1995-12-21 1995-12-21 Clock generating circuit of digital phase locked loop

Country Status (1)

Country Link
KR (1) KR100238747B1 (en)

Also Published As

Publication number Publication date
KR100238747B1 (en) 2000-01-15

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