KR970054524A - Method of manufacturing polycrystalline silicon thin film transistor - Google Patents
Method of manufacturing polycrystalline silicon thin film transistor Download PDFInfo
- Publication number
- KR970054524A KR970054524A KR1019950069700A KR19950069700A KR970054524A KR 970054524 A KR970054524 A KR 970054524A KR 1019950069700 A KR1019950069700 A KR 1019950069700A KR 19950069700 A KR19950069700 A KR 19950069700A KR 970054524 A KR970054524 A KR 970054524A
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- KR
- South Korea
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- thin film
- film transistor
- forming
- ion implantation
- layer pattern
- Prior art date
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- Thin Film Transistor (AREA)
Abstract
이온주입공정을 줄인 다결정실리콘-박막트랜지스터의 제조방법에 대해 기재되어 있다. 본발명의 다결정실리콘-박막트랜지스터의 제조방법은 유리기판상에 소정 크기의 보강층 패턴을 형성하는 단계; 상기 보강층 패턴에 N+형의 도펀트로 1차의 이온주입을 실시하는 단계와, 상기 1차의 이온주입 후, 결과물 전면에 반도체패턴 및, 게이트 절연막을 차례로 형성하는 단계와, 상기 보강층 패턴이 형성되지 않은 게이트절연막위에 소정 크기의 게이트전극을 형성하는 단계와, 및 열처리공정을 통해 상기 1차의 이온주입시에 사용된 N+형의 도펀트를 상기 반도체패턴으로 확산시켜 화소부분 N형 박막 트랜지스터 및 구동회로 부분 N형 박막 트랜지스터의 소오스전극과 드레인 전극을 동시에 형성하는 단계를 구비하여 이루어지는 것을 특징으로 한다.A method for producing a polycrystalline silicon-thin film transistor with reduced ion implantation process is described. Method of manufacturing a polysilicon-thin film transistor of the present invention comprises the steps of forming a reinforcing layer pattern of a predetermined size on a glass substrate; Performing primary ion implantation into the reinforcement layer pattern with an N + type dopant, forming a semiconductor pattern and a gate insulating film on the entire surface of the resultant after the primary ion implantation, and the reinforcement layer pattern is not formed Forming a gate electrode having a predetermined size on the uninsulated gate insulating film, and diffusing an N + type dopant used in the first ion implantation into the semiconductor pattern through a heat treatment process, thereby forming a pixel portion N type thin film transistor and a driving circuit. And simultaneously forming a source electrode and a drain electrode of the partial N-type thin film transistor.
따라서, 본 발명에 의한 다결정실리콘-TFT의 제조방법에 의하면, 스토리전극 형성을 위한 이온주입공정을 이용하여 화소부분 N-TFT 및 구동회로 부분 N-TFT의 소오스전극과 드레인전극을 함께 구현함으로써, 종래에 비해 이온주입공정을 최대 3회 줄일 수 있다.Therefore, according to the method of manufacturing a polysilicon-TFT according to the present invention, by implementing the source electrode and the drain electrode of the pixel portion N-TFT and the driving circuit portion N-TFT together using an ion implantation process for forming a story electrode, Compared with the conventional ion implantation process can be reduced up to three times.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2D도는 본 발명에 따른 다결정 실리콘-TFT의 제조방법을 나타낸 공정순서도.2A to 2D are process flow charts showing a method for producing a polycrystalline silicon-TFT according to the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950069700A KR970054524A (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing polycrystalline silicon thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950069700A KR970054524A (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing polycrystalline silicon thin film transistor |
Publications (1)
Publication Number | Publication Date |
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KR970054524A true KR970054524A (en) | 1997-07-31 |
Family
ID=66639179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950069700A KR970054524A (en) | 1995-12-30 | 1995-12-30 | Method of manufacturing polycrystalline silicon thin film transistor |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100446388B1 (en) * | 1996-12-18 | 2004-11-03 | 비오이 하이디스 테크놀로지 주식회사 | Gate insulating layer structure of tft for preventing short circuit between gate electrode and source/drain electrode and fabricating method thereof |
-
1995
- 1995-12-30 KR KR1019950069700A patent/KR970054524A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100446388B1 (en) * | 1996-12-18 | 2004-11-03 | 비오이 하이디스 테크놀로지 주식회사 | Gate insulating layer structure of tft for preventing short circuit between gate electrode and source/drain electrode and fabricating method thereof |
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