KR970054415A - Semiconductor device having high breakdown voltage and high frequency characteristics and manufacturing method thereof - Google Patents

Semiconductor device having high breakdown voltage and high frequency characteristics and manufacturing method thereof Download PDF

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Publication number
KR970054415A
KR970054415A KR1019950065728A KR19950065728A KR970054415A KR 970054415 A KR970054415 A KR 970054415A KR 1019950065728 A KR1019950065728 A KR 1019950065728A KR 19950065728 A KR19950065728 A KR 19950065728A KR 970054415 A KR970054415 A KR 970054415A
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South Korea
Prior art keywords
impurity layer
semiconductor substrate
conductivity type
layer
concentration
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KR1019950065728A
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Korean (ko)
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KR0175699B1 (en
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이언상
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곽정소
한국전자 주식회사
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Priority to KR1019950065728A priority Critical patent/KR0175699B1/en
Publication of KR970054415A publication Critical patent/KR970054415A/en
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Publication of KR0175699B1 publication Critical patent/KR0175699B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

본 발명은 SDB(silicon direct bonding)을 이용하여 내부 베이스(Intrinsic Base) 영역내에 매입층을 형성하여 저항 성분을 감소시킨 고내압 및 고주파 특성을 갖는 반도체 장치 및 그 제조 방법에 관한 것으로써, 제1전도형의 고농도 불순물층 상에 동형의 저농도 불순물층과 제2전도형의 불순물층이 형성된 제1 반도체 기판; 및, 상기 제1반도체 기판의 상부에 접착되며, 제2전도형의 고농도 불순물층이 하부 표면 근방에 복수개 형성된 제2전도형의 저농도 불순물층 상부에 동형의 고농도 불순물층이 형성되어 있으며, 양측에는 제2전도형의 불순물층이 표면으로부터 제1 반도체 기판의 제2전도형의 불순물층까지 형성된 제2반도체 기판을 포함하여 이루어진 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage and a high frequency characteristic in which a resistance layer is formed by forming a buried layer in an intrinsic base region using silicon direct bonding (SDB), and a method of manufacturing the same. A first semiconductor substrate having a same type of low concentration impurity layer and a second conductivity type impurity layer formed on a conductive high concentration impurity layer; And a high concentration impurity layer of the same type is formed on an upper portion of the second conductivity type low concentration impurity layer, which is attached to an upper portion of the first semiconductor substrate, and a plurality of second conductivity type high concentration impurity layers are formed near the bottom surface. The impurity layer of the second conductivity type includes a second semiconductor substrate formed from the surface to the impurity layer of the second conductivity type of the first semiconductor substrate.

Description

고내압 및 고주파 특성을 갖는 반도체 장치 및 그 제조 방법Semiconductor device having high breakdown voltage and high frequency characteristics and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 다른 고내압 및 고주파 특성을 갖는 트랜지스터의 구조 단면도.1 is a structural cross-sectional view of a transistor having high breakdown voltage and high frequency characteristics according to the present invention.

제2도는 제1도에 도시된 트랜지스터에 사용되는 웨이퍼의 구조 단면도.FIG. 2 is a structural cross-sectional view of the wafer used for the transistor shown in FIG.

Claims (2)

제1전도형의 고농도 불순물층 상에 동형의 저농도 불순물층과 제2전도형의 불순물층이 형성된 제1반도체 기판; 상기 제1반도체 기판의 상부에 접착되며, 제2전도형의 고농도 불순물층이 하부 표면 근방에 복수개 형성된 제2전도형의 저농도 불순물층 상부에 동형의 고농도 불순물층이 형성되어 있으며, 양측에는 제2전도형의 불순물층이 표면으로부터 제1반도체 기판의 제2전도형의 불순물층까지 형성된 제2반도체 기판을 포함하여 이루어진 고내압 및 고주파 특성을 갖는 반도체 장치.A first semiconductor substrate on which a low concentration impurity layer of the same type and an impurity layer of a second conductivity type are formed on the first conductivity type high concentration impurity layer; A high-concentration impurity layer of the same type is formed on the second conductive-type low-concentration impurity layer, which is adhered to an upper portion of the first semiconductor substrate, and a plurality of second-conductive high-concentration impurity layers are formed near the lower surface thereof. A semiconductor device having high breakdown voltage and high frequency characteristics, comprising a second semiconductor substrate having a conductive impurity layer formed from a surface to a second conductive impurity layer of a first semiconductor substrate. 제1전도형의 불순물이 고농도로 도핑된 실리콘 기판의 상부에 동형의 불순물이 저농도로 도핑된 불순물층을 형성하고, 상기 저농도 불순물층의 표면 근방에 제2전도형의 불순물층을 형성한 제1반도체 기판을 제조하는 단계; 제2전도형의 불순물이 고농도로 도핑된 실리콘 기판의 상부에 동형의 불순물이 저농도로 도핑된 불순물층을 형성하고, 상기 저농도 불순물층의 표면 근방에 선택적으로 고농도의 P형 불순물층을 복수개 형성한 제2반도체 기판을 제조하는 단계; 상기 제1반도체 기판의 제2전도형 불순물층이 형성된 면과 제2반도체 기판의 제2전도형의 고농도 불순물층이 복수개 형성된 면을 접착하여 복수개의 제2전도형의 고농도 불순물층을 매몰층으로 형성하고, 제2반도체 기판에 형성된 제2전도형의 저농도 불순물층이 드러나도록 제2전도형의 고농도 불순물층을 폴리싱을 이용 제거하는 단계; 상기 제2 반도체 기판의 제2전도형의 저농도 불순물층 표면 근방에 선택적으로 제1전도형의 불순물층을 형성하는 단계를 포함하여 이루어지는 고내압 및 고주파 특성을 갖는 반도체 장치의 제조 방법.A first impurity layer doped with a low concentration of the same type of impurity on the silicon substrate doped with a high concentration of the first conductivity type impurity, and a first conductive impurity layer formed near the surface of the low concentration impurity layer Manufacturing a semiconductor substrate; An impurity layer doped with a low concentration of the same type of impurities is formed on a silicon substrate doped with a high concentration of the second conductivity type impurities, and a plurality of high concentration P-type impurity layers are selectively formed near the surface of the low concentration impurity layer. Manufacturing a second semiconductor substrate; Bonding a surface on which the second conductive impurity layer of the first semiconductor substrate is formed and a surface on which a plurality of the second conductive impurity concentration layers of the second semiconductor substrate are formed are bonded to the buried layer. Forming and removing the high conductivity impurity layer of the second conductivity type using polishing to expose the second conductivity type impurity layer formed on the second semiconductor substrate; And selectively forming an impurity layer of the first conductivity type near the surface of the second conductivity type low concentration impurity layer of the second semiconductor substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065728A 1995-12-29 1995-12-29 Semiconductor device with a high voltage and high frequency and method for manufacturing the same KR0175699B1 (en)

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KR1019950065728A KR0175699B1 (en) 1995-12-29 1995-12-29 Semiconductor device with a high voltage and high frequency and method for manufacturing the same

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KR1019950065728A KR0175699B1 (en) 1995-12-29 1995-12-29 Semiconductor device with a high voltage and high frequency and method for manufacturing the same

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