JPH06140632A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06140632A JPH06140632A JP28804892A JP28804892A JPH06140632A JP H06140632 A JPH06140632 A JP H06140632A JP 28804892 A JP28804892 A JP 28804892A JP 28804892 A JP28804892 A JP 28804892A JP H06140632 A JPH06140632 A JP H06140632A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- layer
- type
- epitaxial layer
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
縦型ＭＯＳＦＥＴを有するパワーＩＣに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a power IC having a vertical MOSFET.
【０００２】[0002]
【従来の技術】パワーＩＣでは、縦型ＭＯＳＦＥＴとコ
ントロール回路が１チップ上に形成されており、その分
離の為に、エピタキシャル層を２層に積層している。2. Description of the Related Art In a power IC, a vertical MOSFET and a control circuit are formed on one chip, and two epitaxial layers are stacked to separate them.
【０００３】図３は従来の半導体装置の一例を示す断面
図である。FIG. 3 is a sectional view showing an example of a conventional semiconductor device.
【０００４】図３に示すように、Ｎ型シリコン基板１上
に設けたＰ型エピタキシャル層２と、その一部にＮ型不
純物を拡散して設けたＮ型の埋込拡散層３と、埋込拡散
層３を含む表面に設けたＮ型エピタキシャル層４と、Ｎ
型エピタキシャル層４に設けたＰ型の素子分離層５を有
しており、素子分離層５で分離されたＮ型エピタキシャ
ル層４内にＰ型ウェル８及びＰ型ベース領域９とを設
け、ベース領域９内にゲート電極１１に整合してＮ型ソ
ース領域１０を設けて縦型ＭＯＳＦＥＴを形成する。ま
た、絶縁膜７に設けたコンタクト孔を介してＮ型ソース
領域１０及びＰ型ウェルを接続するソース電極１２と素
子分離層５と接続する引出電極１３が設けられる。As shown in FIG. 3, a P-type epitaxial layer 2 provided on an N-type silicon substrate 1, an N-type buried diffusion layer 3 provided by diffusing N-type impurities in a part thereof, and a buried type An N-type epitaxial layer 4 provided on the surface including the diffusion layer 3;
A P type well 8 and a P type base region 9 are provided in the N type epitaxial layer 4 separated by the element separating layer 5. An N-type source region 10 is provided in the region 9 in alignment with the gate electrode 11 to form a vertical MOSFET. In addition, a source electrode 12 that connects the N-type source region 10 and the P-type well and a lead electrode 13 that connects the element isolation layer 5 are provided through a contact hole provided in the insulating film 7.
【０００５】ここで、素子分離層５とＮ型エピタキシャ
ル層４を逆バイアスすることで、縦型ＭＯＳＦＥＴとコ
ントロール回路は電気的に分離される。By reverse biasing the element isolation layer 5 and the N-type epitaxial layer 4, the vertical MOSFET and the control circuit are electrically isolated.
【０００６】次に、縦型ＭＯＳＦＥＴの動作について説
明する。通常の動作において、ドレイン電極１４にはプ
ラス電位を印加し、ソース電極１２を接地する。ここ
で、ゲート電極１１にプラス電位を与えると、Ｐ型ベー
ス領域９の表面にＮ型反転層が形成され、電流がドレイ
ン電極１４からＮ型シリコン基板１，Ｎ型埋込拡散層
３，Ｎ型エピタキシャル層４，Ｐ型ベース領域９の表面
Ｎ型反転層，Ｎ型ソース領域１０を順に通り、ソース電
極１２に流れる。Next, the operation of the vertical MOSFET will be described. In normal operation, a positive potential is applied to the drain electrode 14 and the source electrode 12 is grounded. Here, when a positive potential is applied to the gate electrode 11, an N-type inversion layer is formed on the surface of the P-type base region 9, and a current flows from the drain electrode 14 to the N-type silicon substrate 1, the N-type buried diffusion layer 3, and N. It flows through the type epitaxial layer 4, the surface N type inversion layer of the P type base region 9, and the N type source region 10 in this order to the source electrode 12.
【０００７】縦型ＦＥＴの使用例として、コイルなどの
誘導性負荷を駆動する場合がある。この動作を縦型ＭＯ
ＳＦＥＴの等価回路図４を用いて説明する。トランジス
タＱ1 がオンしている場合、電流Ｉ1 が流れる。次にゲ
ート１１をローレベルにして、トランジスタＱ1 をオフ
した場合、Ｉ1 はただちに流れなくなるが、誘導性負荷
の逆起電力によって、ダイオードＤ1 ，Ｄ2 をブレーク
ダウンさせ、電流Ｉ2，Ｉ3 ，Ｉ4 が流れる。As an example of using the vertical FET, there is a case of driving an inductive load such as a coil. This operation is vertical MO
An equivalent circuit of the SFET will be described with reference to FIG. When the transistor Q 1 is on, the current I 1 flows. Next, when the gate 11 is turned to the low level and the transistor Q 1 is turned off, I 1 stops flowing immediately, but the back electromotive force of the inductive load causes the diodes D 1 and D 2 to break down and the current I 2 , I 3 and I 4 flow.
【０００８】ここで、Ｉ3 は寄生ＮＰＮトランジスタＱ
2 のベースに流れるため、トランジスタをオンさせ、素
子を破壊させることがある。これをふせぐために一般に
ベース抵抗Ｒ2 を小さくする事がおこなわれている。ま
た、ダイオードＤ2 は、コントロール回路と縦型ＭＯＳ
ＦＥＴを完全に分離するために、ダイオード１７よりも
高い逆耐圧をもつ様に通常設計される。このため、逆起
電力によって流れる電流は主にＩ2 ，Ｉ3 となる。Where I 3 is a parasitic NPN transistor Q
Since it flows to the base of No. 2 , it may turn on the transistor and destroy the device. In order to prevent this, the base resistance R 2 is generally reduced. Further, the diode D 2 is a control circuit and a vertical MOS.
It is usually designed to have a higher reverse breakdown voltage than the diode 17 in order to completely isolate the FET. Therefore, the currents flowing by the counter electromotive force are mainly I 2 and I 3 .
【０００９】[0009]
【発明が解決しようとする課題】この従来の半導体装置
では、縦型ＭＯＳＦＥＴを用いて誘導性負荷を駆動する
場合、逆起電力によって、トランジスタが破壊するとい
う問題があった。This conventional semiconductor device has a problem in that when a vertical MOSFET is used to drive an inductive load, the transistor is destroyed by the back electromotive force.
【００１０】[0010]
【課題を解決するための手段】本発明の第１の半導体装
置は、一導電型半導体基板の一主面に設けた逆導電型エ
ピタキシャル層と、前記逆導電型エピタキシャル層に設
けて前記半導体基板に達する一導電型埋込拡散層と、前
記一導電型拡散層を含む表面に設けた一導電型エピタキ
シャル層と、前記一導電型エピタキシャル層に設けて前
記逆導電型エピタキシャル層に達する逆導電型の素子分
離層と、前記素子分離層で分離された前記一導電型エピ
タキシャル層内に設けた逆導電型のベース領域と、前記
ベース領域内に設けた一導電型のソース領域とを有する
半導体装置において、分離された前記一導電型エピタキ
シャル層内の前記素子分離層に接して設けた一導電型の
高濃度拡散層を有する。According to a first semiconductor device of the present invention, a reverse conductivity type epitaxial layer is provided on one main surface of a one conductivity type semiconductor substrate, and the semiconductor substrate is provided on the reverse conductivity type epitaxial layer. To the first conductivity type buried diffusion layer, a single conductivity type epitaxial layer provided on the surface including the first conductivity type diffusion layer, and a reverse conductivity type reaching the reverse conductivity type epitaxial layer provided in the first conductivity type epitaxial layer. A semiconductor device having a device isolation layer, a base region of opposite conductivity type provided in the epitaxial layer of one conductivity type separated by the device isolation layer, and a source region of one conductivity type provided in the base region. In the separated one-conductivity-type epitaxial layer, the one-conductivity-type high-concentration diffusion layer provided in contact with the element isolation layer.
【００１１】本発明の第２の半導体装置は、一導電型半
導体基板の一主面に設けた逆導電型エピタキシャル層
と、前記逆導電型エピタキシャル層に設けて前記半導体
基板に達する一導電型埋込拡散層と、前記一導電型拡散
層を含む表面に設けた一導電型エピタキシャル層と、前
記一導電型エピタキシャル層に設けて前記逆導電型エピ
タキシャル層に達する逆導電型の素子分離層と、前記素
子分離層で分離された前記一導電型エピタキシャル層内
に設けた逆導電型のベース領域と、前記ベース領域内に
設けた一導電型のソース領域とを有する半導体装置にお
いて、前記逆導電型エピタキシャル層内の前記一導電型
埋込拡散層及び前記素子分離層に接して設けた一導電型
の高濃度埋込拡散層を有する。A second semiconductor device of the present invention comprises a reverse conductivity type epitaxial layer provided on one main surface of a conductivity type semiconductor substrate, and a conductivity type buried layer reaching the semiconductor substrate by being provided on the reverse conductivity type epitaxial layer. Embedded diffusion layer, one conductivity type epitaxial layer provided on the surface including the one conductivity type diffusion layer, a reverse conductivity type element isolation layer provided in the one conductivity type epitaxial layer to reach the reverse conductivity type epitaxial layer, A semiconductor device having a base region of opposite conductivity type provided in the epitaxial layer of one conductivity type separated by the element isolation layer, and a source region of one conductivity type provided in the base region, wherein the opposite conductivity type is provided. The semiconductor device includes a one-conductivity-type buried diffusion layer provided in contact with the one-conductivity-type buried diffusion layer and the element isolation layer in an epitaxial layer.
【００１２】[0012]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１３】図１は本発明の第１の実施例を示す断面図
である。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【００１４】図１に示すように、Ｎ型シリコン基板１の
上に設けたＰ型エピタキシャル層２に選択的にＮ型不純
物を拡散して設け且つＮ型シリコン基板１と接続するＮ
型埋込拡散層３と、Ｎ型埋込層３を含む表面に設けたＮ
型エピタキシャル層４と、Ｎ型エピタキシャル層４に設
けてＰ型エピタキシャル層２に達するＰ型の素子分離層
５と、素子分離層５により区画された素子形成領域内に
設けたＰ型ベース領域９及びＰ型ウェル８と、Ｐ型ベー
ス領域９上に絶縁膜７を介して設けたゲート電極１１に
整合してＰ型ベース領域９内に設けたＮ型ソース領域１
０と、Ｎ型エピタキシャル層４内の素子分離層５に接し
て設けたＮ型不純物を高濃度にドープしたＮ+ 型拡散層
６と、Ｎ型ソース領域１０とＰ型ウェル８を接続するソ
ース電極１２と、素子分離層５に接続する引出電極１３
と、Ｎ型シリコン基板１の下面に設けたドレイン電極１
４を有して構成されている。As shown in FIG. 1, an N-type impurity is selectively diffused in the P-type epitaxial layer 2 provided on the N-type silicon substrate 1 and connected to the N-type silicon substrate 1.
Type buried diffusion layer 3 and N provided on the surface including the N type buried layer 3
Type epitaxial layer 4, P type element isolation layer 5 provided on N type epitaxial layer 4 and reaching P type epitaxial layer 2, and P type base region 9 provided in an element formation region partitioned by element isolation layer 5. And the N-type source region 1 provided in the P-type base region 9 in alignment with the P-type well 8 and the gate electrode 11 provided on the P-type base region 9 via the insulating film 7.
0, an N + type diffusion layer 6 provided in contact with the element isolation layer 5 in the N type epitaxial layer 4 and heavily doped with N type impurities, a source connecting the N type source region 10 and the P type well 8 Electrode 12 and extraction electrode 13 connected to element isolation layer 5
And the drain electrode 1 provided on the lower surface of the N-type silicon substrate 1.
4 is configured.
【００１５】ここで、Ｎ+ 型拡散層６と素子分離層５の
間に作られるダイオードはＰ型ベース領域９とＮ型エピ
タキシャル層４の間に作られるダイオードよりも逆耐圧
が低くなる様に作られる。Here, the diode formed between the N + type diffusion layer 6 and the element isolation layer 5 has a lower reverse breakdown voltage than the diode formed between the P type base region 9 and the N type epitaxial layer 4. Made
【００１６】本実施例のパワーＩＣの縦型ＭＯＳトラン
ジスタに、誘電性負荷を接続した場合の動作は図４に示
す等価回路のトランジスタＱ1 がオフしたあと、ドレイ
ン電極１４の電位が上昇していくと、ダイオードＤ1 ，
Ｄ2 には逆バイアスがかかっていく。本実施例では、Ｎ
+ 型拡散層６によってダイオードＤ2 の逆耐圧はダイオ
ードＤ1 よりも低く設計されているため、先にダイオー
ドＤ2 がブレークダウンしてＩ4 が流れ始める。Ｉ4 が
流れることで、Ｉ2 ，Ｉ3 は殆ど流れず、よってＮＰＮ
トランジスタＱ2 のベースがバイアスされないため、ト
ランジスタの破壊がおこらない。When a dielectric load is connected to the vertical MOS transistor of the power IC of this embodiment, the operation of the equivalent circuit shown in FIG. 4 is such that the transistor Q 1 is turned off and the potential of the drain electrode 14 rises. As you go, the diode D 1 ,
Reverse bias is applied to D 2 . In this embodiment, N
+ Since the inverse breakdown voltage of the diode D 2 by type diffusion layer 6 is designed to be lower than the diode D 1, above the diode D 2 begins I 4 to break down the flow. Since I 4 flows, I 2 and I 3 hardly flow, and thus the NPN
Since the base of the transistor Q 2 is not biased, the transistor will not be destroyed.
【００１７】図２は本発明の第２の実施例を示す断面図
である。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【００１８】図２に示すように、図１のＮ+ 型拡散層６
の代りにＮ+ 型埋込拡散層１５をＰ型エピタキシャル層
２に設けてＮ型埋込拡散層３と素子分離層５との間でダ
イオードＤ2 を形成している以外は第１の実施例と同様
の構成を示しており、第１の実施例と同様の効果を有す
る。As shown in FIG. 2, the N + type diffusion layer 6 of FIG.
In the first embodiment except that the N + type buried diffusion layer 15 is provided in the P type epitaxial layer 2 instead of the above to form the diode D 2 between the N type buried diffusion layer 3 and the element isolation layer 5. The structure is similar to that of the example, and has the same effect as that of the first embodiment.
【００１９】[0019]
【発明の効果】以上説明したように本発明は、縦型ＭＯ
ＳＦＥＴの外周部に、耐圧の低いダイオードを作り込む
ことによって、誘導性負荷を駆動するときに生ずる逆起
電力によるトランジスタの破壊を防止することができる
という効果を有する。As described above, according to the present invention, the vertical MO
By forming a diode having a low breakdown voltage on the outer peripheral portion of the SFET, it is possible to prevent the breakdown of the transistor due to the counter electromotive force generated when driving the inductive load.
【図１】本発明の第１の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図３】従来の半導体装置の一例を示す断面図。FIG. 3 is a sectional view showing an example of a conventional semiconductor device.
【図４】縦型ＭＯＳＦＥＴの等価回路図。FIG. 4 is an equivalent circuit diagram of a vertical MOSFET.
１ Ｎ型シリコン基板 ２ Ｐ型エピタキシャル層 ３ Ｎ型埋込拡散層 ４ Ｎ型エピタキシャル層 ５ 素子分離層 ６ Ｎ+ 型拡散層 ７ Ｐ型ベース領域 ８ Ｐ型ウェル ９ Ｐ型ベース領域 １０ Ｎ型ソース領域 １１ ゲート電極 １２ ソース電極 １３ 引出電極 １４ ドレイン電極 １５ Ｎ+ 型埋込拡散層1 N-type silicon substrate 2 P-type epitaxial layer 3 N-type buried diffusion layer 4 N-type epitaxial layer 5 Element isolation layer 6 N + type diffusion layer 7 P-type base region 8 P-type well 9 P-type base region 10 N-type source Region 11 Gate electrode 12 Source electrode 13 Extraction electrode 14 Drain electrode 15 N + type buried diffusion layer
Claims (2)
導電型エピタキシャル層と、前記逆導電型エピタキシャ
ル層に設けて前記半導体基板に達する一導電型埋込拡散
層と、前記一導電型拡散層を含む表面に設けた一導電型
エピタキシャル層と、前記一導電型エピタキシャル層に
設けて前記逆導電型エピタキシャル層に達する逆導電型
の素子分離層と、前記素子分離層で分離された前記一導
電型エピタキシャル層内に設けた逆導電型のベース領域
と、前記ベース領域内に設けた一導電型のソース領域と
を有する半導体装置において、分離された前記一導電型
エピタキシャル層内の前記素子分離層に接して設けた一
導電型の高濃度拡散層を有することを特徴とする半導体
装置。1. A reverse conductivity type epitaxial layer provided on one main surface of a conductivity type semiconductor substrate, a buried conductivity diffusion layer reaching the semiconductor substrate by being provided on the reverse conductivity type epitaxial layer, and the conductivity type. The one conductivity type epitaxial layer provided on the surface including the type diffusion layer, the opposite conductivity type element isolation layer which is provided on the one conductivity type epitaxial layer and reaches the opposite conductivity type epitaxial layer, and the element isolation layer In a semiconductor device having a base region of opposite conductivity type provided in the one conductivity type epitaxial layer and a source region of one conductivity type provided in the base region, the semiconductor device in the separated one conductivity type epitaxial layer A semiconductor device having a high-concentration diffusion layer of one conductivity type provided in contact with an element isolation layer.
導電型エピタキシャル層と、前記逆導電型エピタキシャ
ル層に設けて前記半導体基板に達する一導電型埋込拡散
層と、前記一導電型拡散層を含む表面に設けた一導電型
エピタキシャル層と、前記一導電型エピタキシャル層に
設けて前記逆導電型エピタキシャル層に達する逆導電型
の素子分離層と、前記素子分離層で分離された前記一導
電型エピタキシャル層内に設けた逆導電型のベース領域
と、前記ベース領域内に設けた一導電型のソース領域と
を有する半導体装置において、前記逆導電型エピタキシ
ャル層内の前記一導電型埋込拡散層及び前記素子分離層
に接して設けた一導電型の高濃度埋込拡散層を有するこ
とを特徴とする半導体装置。2. An opposite conductivity type epitaxial layer provided on one main surface of a one conductivity type semiconductor substrate, one conductivity type buried diffusion layer reaching the semiconductor substrate by being provided on the opposite conductivity type epitaxial layer, and the one conductivity type. The one conductivity type epitaxial layer provided on the surface including the type diffusion layer, the opposite conductivity type element isolation layer which is provided on the one conductivity type epitaxial layer and reaches the opposite conductivity type epitaxial layer, and the element isolation layer A semiconductor device having a base region of opposite conductivity type provided in the epitaxial layer of one conductivity type and a source region of one conductivity type provided in the base region, wherein the one conductivity type in the epitaxial layer of the opposite conductivity type A semiconductor device comprising a buried diffusion layer and a high conductivity buried diffusion layer of one conductivity type provided in contact with the element isolation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28804892A JP2871352B2 (en) | 1992-10-27 | 1992-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28804892A JP2871352B2 (en) | 1992-10-27 | 1992-10-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06140632A true JPH06140632A (en) | 1994-05-20 |
| JP2871352B2 JP2871352B2 (en) | 1999-03-17 |
Family
ID=17725164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28804892A Expired - Fee Related JP2871352B2 (en) | 1992-10-27 | 1992-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871352B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1022785A1 (en) * | 1999-01-25 | 2000-07-26 | STMicroelectronics S.r.l. | Electronic semiconductor power device with integrated diode |
| KR100648276B1 (en) * | 2004-12-15 | 2006-11-23 | 삼성전자주식회사 | Vdmos device incorporating reverse diode |
| US7936003B2 (en) | 2005-02-03 | 2011-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device having transistor with vertical gate electrode and method of fabricating the same |
-
1992
- 1992-10-27 JP JP28804892A patent/JP2871352B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1022785A1 (en) * | 1999-01-25 | 2000-07-26 | STMicroelectronics S.r.l. | Electronic semiconductor power device with integrated diode |
| US6222248B1 (en) | 1999-01-25 | 2001-04-24 | Stmicroelectronics S.R.L. | Electronic semiconductor power device with integrated diode |
| USRE40222E1 (en) * | 1999-01-25 | 2008-04-08 | Stmicroelectronics S.R.L. | Electronic semiconductor power device with integrated diode |
| KR100648276B1 (en) * | 2004-12-15 | 2006-11-23 | 삼성전자주식회사 | Vdmos device incorporating reverse diode |
| US7417282B2 (en) | 2004-12-15 | 2008-08-26 | Samsung Electronics, Co., Ltd. | Vertical double-diffused metal oxide semiconductor (VDMOS) device incorporating reverse diode |
| US7936003B2 (en) | 2005-02-03 | 2011-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device having transistor with vertical gate electrode and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2871352B2 (en) | 1999-03-17 |
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