KR970054327A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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Publication number
KR970054327A
KR970054327A KR1019950049820A KR19950049820A KR970054327A KR 970054327 A KR970054327 A KR 970054327A KR 1019950049820 A KR1019950049820 A KR 1019950049820A KR 19950049820 A KR19950049820 A KR 19950049820A KR 970054327 A KR970054327 A KR 970054327A
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KR
South Korea
Prior art keywords
oxide
layer
spacer
semiconductor device
oxide film
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KR1019950049820A
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Korean (ko)
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KR100191770B1 (en
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한준호
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김광호
삼성전자 주식회사
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Priority to KR1019950049820A priority Critical patent/KR100191770B1/en
Publication of KR970054327A publication Critical patent/KR970054327A/en
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Publication of KR100191770B1 publication Critical patent/KR100191770B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

게이트폴리층의 노출을 방지하기 위해 폴리사이드 구조의 측벽에 2중 스페이서가 형성된 반도체소자 및 그 제조방법이 개시되어 있다.Disclosed are a semiconductor device having a double spacer formed on sidewalls of a polyside structure and a method of manufacturing the same to prevent exposure of the gate poly layer.

본 발명은 반도체기판상에 게이트절연층을 개재하여 게이트폴리층과 금속실리사이드층이 패턴화되어 이루어지는 폴리사이드 구조를 갖는 반도체소자에서 상기 폴리사이드 구조의 측벽을 따라 제1산화막 스페이서와 제2산화막 스페이서가 수직으로 연이어 형성되어 있으며, 이를 제조하는 방법이다.The present invention provides a semiconductor device having a polyside structure in which a gate poly layer and a metal silicide layer are patterned through a gate insulating layer on a semiconductor substrate. Is formed vertically and successively, which is a method of manufacturing the same.

따라서, 후속공정에 의해 금속실리사이드층의 리프팅이 방지되어 소자의 신뢰성이 향상되고, 소자의 미세화를 촉진시키는 효과가 있다.Therefore, the lifting of the metal silicide layer is prevented by the subsequent process, thereby improving the reliability of the device and promoting the miniaturization of the device.

Description

반도체소자 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 내지 제5도는 본 발명의 일 실시예에 따른 반도체소자의 제조과정을 나타내는 단면도들이다.3 to 5 are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

Claims (6)

반도체기판상에 게이트절연층을 개재하여 게이트폴리층과 금속실리사이드층이 패턴화되어 이루어지는 폴리사이드 구조를 갖는 반도체소자에 있어서, 상기 폴리사이드 구조의 측벽을 따라 제1산화막 스페이서와 제2산화막 스페이서가 수직으로 연이어 형성되어 있는 것을 특징으로 하는 반도체소자.In a semiconductor device having a polyside structure in which a gate poly layer and a metal silicide layer are patterned through a gate insulating layer on a semiconductor substrate, a first oxide spacer and a second oxide spacer are formed along sidewalls of the polyside structure. A semiconductor device, characterized in that formed in succession. 제1항에 있어서, 상기 게이트폴리층 측벽을 따라 제1산화막 스페이서가 형성되어 있으며, 상기 금속실리사이드층 측벽을 따라 상기 제1산화막 스페이서상으로 제2산화막 스페이서가 형성되어 있는 것을 특징으로 하는 상기 반도체소자.The semiconductor device of claim 1, wherein a first oxide spacer is formed along the sidewall of the gate poly layer, and a second oxide spacer is formed on the first oxide spacer along the sidewall of the metal silicide layer. device. 제1항 또는 제2항에 있어서, 상기 제1산화막 스페이서는 상기 제2산화막 스레이서에 비하여 식각속도가 빠른 물질로 이루어진 것을 특징으로 하는 상기 반도체소자.The semiconductor device of claim 1, wherein the first oxide spacer is made of a material having a higher etching rate than the second oxide layer spacer. 제1항에 있어서, 상기 금속실리사이드층은 텅스텐실리사이드층임을 특징으로 하는 상기 반도체소자.The semiconductor device of claim 1, wherein the metal silicide layer is a tungsten silicide layer. 반도체기판상에 게이트절연층을 개재하여 게이트폴리층과 금속실리사이드층이 패턴화되어 이루어지는 폴리사이드 구조의 측벽에 스페이서를 형성하는 반도체소자의 제조방법에 있어서, 상기 반도체기판상의 폴리사이드 구조의 측벽을 따라 제1산화막을 소정의 높이가 되도록 부분적으로 형성하는 단계; 상기 제1산화막상을 포함하여 기판 전면에 상기 제1산화막 보다 식각속도가 작은 제2산화막을 형성하는 단계; 상기 제1산화막이 노출될 때까지 상기 제2산화막을 에치백하여 상기 폴리사이드 구조의 상측에 제2산화막 스페이서를 형성하는 단계; 및 상기 노출된 제1산화막을 식각하여 상기 제2산화막 스페이서 하부의 상기 폴리사이드 구조 측벽에 제1산화막 스페이서를 형성하는 단계를 구비하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.A method of manufacturing a semiconductor device in which a spacer is formed on a sidewall of a polyside structure in which a gate poly layer and a metal silicide layer are patterned through a gate insulating layer on a semiconductor substrate. Accordingly partially forming the first oxide film to have a predetermined height; Forming a second oxide film having an etching rate lower than that of the first oxide film on the entire surface of the substrate including the first oxide film; Etching back the second oxide layer until the first oxide layer is exposed to form a second oxide spacer on the polyside structure; And etching the exposed first oxide film to form a first oxide film spacer on a sidewall of the polyside structure under the second oxide film spacer. 제5항에 있어서, 상기 제1산화막의 높이는 상기 폴리사이드 구조의 게이트폴리층의 높이로 평탄하게 형성시키는 것을 특징으로 하는 상기 반도체소자의 제조방법.The method of claim 5, wherein a height of the first oxide layer is formed to be equal to a height of the gate poly layer having the polyside structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950049820A 1995-12-14 1995-12-14 Semiconductor device and manufacturing method thereof KR100191770B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950049820A KR100191770B1 (en) 1995-12-14 1995-12-14 Semiconductor device and manufacturing method thereof

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Application Number Priority Date Filing Date Title
KR1019950049820A KR100191770B1 (en) 1995-12-14 1995-12-14 Semiconductor device and manufacturing method thereof

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KR970054327A true KR970054327A (en) 1997-07-31
KR100191770B1 KR100191770B1 (en) 1999-07-01

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