KR970054235A - Flash memory cell manufacturing method - Google Patents

Flash memory cell manufacturing method Download PDF

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Publication number
KR970054235A
KR970054235A KR1019950058467A KR19950058467A KR970054235A KR 970054235 A KR970054235 A KR 970054235A KR 1019950058467 A KR1019950058467 A KR 1019950058467A KR 19950058467 A KR19950058467 A KR 19950058467A KR 970054235 A KR970054235 A KR 970054235A
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KR
South Korea
Prior art keywords
oxide film
film
forming
high voltage
flash memory
Prior art date
Application number
KR1019950058467A
Other languages
Korean (ko)
Inventor
김군성
한성오
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950058467A priority Critical patent/KR970054235A/en
Publication of KR970054235A publication Critical patent/KR970054235A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 산화 절연막으로 셀 스페이서를 형성하여 식각비에 의해 발생되는 언더 컷을 방지하여 각 폴리실리콘층간의 절연 특성 향상, 장애 방지 및 체크 보드를 방지할 수 있는 플래쉬 메모리 셀 제조 방법이 개시된다.The present invention discloses a method of manufacturing a flash memory cell capable of forming a cell spacer with an oxide insulating layer to prevent undercuts caused by an etch ratio, thereby improving insulation properties, preventing failures, and preventing check boards between the polysilicon layers.

Description

플래쉬 메모리 셀 제조 방법Flash memory cell manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A 내지 2E도는 본 발명에 따른 플래쉬 메모리 셀 제조 방법을 설명하기 위한 단면도.2A through 2E are cross-sectional views illustrating a method of manufacturing a flash memory cell according to the present invention.

Claims (2)

플래쉬 메모리 셀 제조 방법에 있어서, 실리콘 기판 상에 터널 산화막, 제1폴리 실리콘층 및 ONO 막으로 적층된 플로팅 게이트를 형성하고, 상기 전체 상부에 제2폴리 실리콘층 및 MTO 막으로 적층된 컨트롤 게이트를 형성하는 단계와, 상기 전체 구조 상부에 제1산화막을 증착한 후, 패턴화 된 제1감광막을 고전압용 마스크로 사용하여 제1산화막을 건식 식각 공정에 의해 식각한 후, 고전압 영역의 제1산화막을 습식 식각으로 제거하는 단계와, 상기 고전압 영역에 고전압 게이트용 제2산화막을 형성하고, 상기 고전압용 마스크인 제1감광막을 제거하는 단계와, 상기 전체 구조 상부에 제2감광막을 도포하고, 상기 제2감광막 패턴이 셀 스페이서용 마스크로 사용하여 제1산화막을 건식 식각 공정으로 식각하는 단계와, 상기 제1산화막을 습식 식각 공정으로 셀 스페이서를 형성한 후, 상기 제2감광막을 제거한 후, 전체 구조 상부에 제3폴리 실리콘층을 형성하는 것을 특징으로 하는 플래쉬 메모리 셀 제조 방법.A method of manufacturing a flash memory cell, comprising: forming a floating gate stacked on a silicon substrate with a tunnel oxide film, a first polysilicon layer, and an ONO film, and a control gate stacked with a second polysilicon layer and an MTO film on the whole. Forming a first oxide film over the entire structure, and etching the first oxide film by a dry etching process using the patterned first photoresist film as a high voltage mask, followed by a first oxide film in a high voltage region. Removing by wet etching, forming a second oxide film for a high voltage gate in the high voltage region, removing the first photoresist film, which is the high voltage mask, applying a second photoresist film on the entire structure, and Etching the first oxide film by a dry etching process using the second photoresist pattern as a mask for the cell spacer, and using the first oxide film by a wet etching process And forming a third polysilicon layer on the entire structure after removing the second photoresist film after forming the spacer. 제1항에 있어서, 상기 제1산화막은 130±30A의 두께가 남을 정도로 식각하는 것을 특징으로 하는 플래쉬 이이피롬 셀 제조 방법.2. The method of claim 1, wherein the first oxide layer is etched to a thickness of 130 ± 30 A. 3. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058467A 1995-12-27 1995-12-27 Flash memory cell manufacturing method KR970054235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058467A KR970054235A (en) 1995-12-27 1995-12-27 Flash memory cell manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058467A KR970054235A (en) 1995-12-27 1995-12-27 Flash memory cell manufacturing method

Publications (1)

Publication Number Publication Date
KR970054235A true KR970054235A (en) 1997-07-31

Family

ID=66619577

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058467A KR970054235A (en) 1995-12-27 1995-12-27 Flash memory cell manufacturing method

Country Status (1)

Country Link
KR (1) KR970054235A (en)

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