KR19980057141A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19980057141A KR19980057141A KR1019960076411A KR19960076411A KR19980057141A KR 19980057141 A KR19980057141 A KR 19980057141A KR 1019960076411 A KR1019960076411 A KR 1019960076411A KR 19960076411 A KR19960076411 A KR 19960076411A KR 19980057141 A KR19980057141 A KR 19980057141A
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- Prior art keywords
- insulating film
- conductive layer
- film
- insulating
- etching
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000003475 lamination Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 분야1. Fields to which the invention described in the claims belong
반도체 소자 제조.Semiconductor device manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
도전층간의 브릿지를 유발시킴으로써 소자의 신뢰성을 저하시키는 문제점을 해결하기 위함.To solve the problem of lowering the reliability of the device by causing the bridge between the conductive layers.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
이중 절연막 스페이서를 형성하여 습식식각시 원치않는 부분에서의 절연막의 손상을 방지하여 도전층간의 브릿지가 발생하는 것을 막음.Formation of double insulating film spacer prevents damage of insulating film in unwanted part during wet etching and prevents bridge between conductive layers.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 메모리 소자의 제조에 이용됨.Used in the manufacture of semiconductor memory devices.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 다결정실리콘과 산화막을 포함한 적층구조와 소정의 도전층과의 브릿지(bridge) 발생을 방지하는 반도체장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which prevents the generation of a bridge between a laminated structure including polycrystalline silicon and an oxide film and a predetermined conductive layer.
반도체장치를 제조하기 위해서는 다층의 도전층 및 절연층등이 사용되는데 절연되어야 할 부분에서 두 도전층간에 브릿지가 발생하여 소자 불량을 유발하는 경우가 있다. 이를 도 1A 내지 도 1D를 참조하여 설명하면 다음과 같다.In order to manufacture a semiconductor device, a multilayer conductive layer, an insulating layer, and the like are used. In some cases, a bridge is generated between two conductive layers in an area to be insulated, causing device defects. This will be described with reference to FIGS. 1A to 1D as follows.
먼저, 도 1A는 반도체기판(1)상에 제1절연막(2)과, 제1도전층(3), 제2절연막(4) 및 제2도전층(5)이 차례로 형성된 적층구조를 나타낸다. 이와 같이 적층구조가 형성된 반도체기판(1) 전면에 도 1B와 같이 제3절연막(6)과 질화막(7)을 차례로 형성한 후, 그위에 감광막을 도포하고 이를 선택적으로 노광 및 현상하여 소정의 감광막패턴(8)을 형성한다.First, FIG. 1A illustrates a lamination structure in which a first insulating film 2, a first conductive layer 3, a second insulating film 4, and a second conductive layer 5 are sequentially formed on a semiconductor substrate 1. As described above, the third insulating film 6 and the nitride film 7 are sequentially formed on the entire surface of the semiconductor substrate 1 having the stacked structure as shown in FIG. 1B, and then a photosensitive film is applied thereon and selectively exposed and developed to provide a predetermined photosensitive film. The pattern 8 is formed.
이어서 도 1C와 같이 상기 감광막패턴(8)을 마스크로 이용하여 상기 질화막(7)을 건식식각하여 상기 적층구조의 일측면에 질화막 스페이서(7')를 형성하고, 습식식각을 행하여 상기 질화막(7) 하부의 제3절연막(6)을 제거한다. 이때, 제3절연막(6)의 습식식각시 질화막 스페이서(7') 하부의 제3절연막 부위(A)가 보호받지 못하고 식각되는 경우가 발생한다.Subsequently, as shown in FIG. 1C, the nitride film 7 is dry-etched using the photoresist pattern 8 as a mask to form a nitride film spacer 7 ′ on one side of the stacked structure, and wet etching is performed to form the nitride film 7. ) The lower third insulating film 6 is removed. In this case, when the wet etching of the third insulating layer 6 occurs, the third insulating layer portion A under the nitride spacer 7 'may be etched without being protected.
다음에 도 1D와 같이 기판 전면에 제3도전층(9)을 형성하게 되면, 상기 제1도전층(2)과 제3도전층(9)이 절연막에 의해 분리되어야 하는데도 불구하고 상기 질화막 스페이서(7') 하부의 제3절연막의 손상으로 인해 (A')에서 보이는 것처럼 제1도전층(2)과 제3도전층(9)이 서로 연결되어 브릿지를 유발시킴으로써 소자의 신뢰성에 저하시키는 문제가 발생할 수 있다.Next, when the third conductive layer 9 is formed on the entire surface of the substrate as shown in FIG. 1D, the nitride spacers may be formed even though the first conductive layer 2 and the third conductive layer 9 should be separated by an insulating film. 7 ') the first conductive layer 2 and the third conductive layer 9 are connected to each other to cause a bridge as shown in (A') due to the damage of the lower third insulating film, thereby lowering the reliability of the device. May occur.
본 발명은 이중 절연막 스페이서를 형성하여 습식식각시 원치않은 부분에서의 절연막의 손상을 방지하여 도전층간의 브릿지가 발생하는 것을 막는 반도체장치의 제조방법을 제공하는 것을 그 목적으로 한다.It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a double insulating film spacer is formed to prevent damage to the insulating film in an unwanted portion during wet etching, thereby preventing the bridge between conductive layers from occurring.
상기 목적을 달성하기 위한 본 발명의 반도체장치 제조방법은 다층의 도전층 및 절연층으로 이루어진 적층구조가 형성된 반도체기판 전면에 제1절연막을 형성하는 단계와, 상기 제1절연막을 선택적으로 식각하여 상기 적층구조의 일측면에 제1절연막 스페이서를 형성하는 단계, 상기 기판 전면에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 식각하여 상기 적층구조 일측면의 상기 제1절연막 스페이서 측면상에 제2절연막 스페이서를 형성하는 단계, 습식식각에 의해 노출된 제1절연막 부위를 제거하는 단계, 및 기판 전면에 도전층을 형성하는 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention for achieving the above object is formed by forming a first insulating film on the entire surface of the semiconductor substrate having a laminated structure consisting of a multi-layer conductive layer and an insulating layer, by selectively etching the first insulating film Forming a first insulating film spacer on one side of the stack structure, forming a second insulating film on the entire surface of the substrate, and selectively etching the second insulating film on the side of the first insulating film spacer on one side of the stack structure Forming a second insulating film spacer; removing the first insulating film portion exposed by wet etching; and forming a conductive layer on the entire surface of the substrate.
도 1A 내지 도 1D는 종래기술에 의한 반도체장치 제조방법을 나타낸 공정순서도,1A to 1D are process flowcharts showing a semiconductor device manufacturing method according to the prior art;
도 2A 내지 도 2E는 본 발명에 의한 반도체장치 제조방법을 나타낸 공정순서도.2A to 2E are process flowcharts showing a method for manufacturing a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 반도체기판, 2 : 제1도전층, 3 : 제1절연막, 4 : 제2도전층, 5 : 제2절연막, 11 : 제3절연막, 11' : 제3절연막 스페이서, 12, 14 : 감광막패턴, 13 : 질화막, 15 : 제3도전층DESCRIPTION OF SYMBOLS 1 Semiconductor board, 2nd 1st conductive layer, 3rd 1st insulating film, 4nd 2nd conductive layer, 5nd 2nd insulating film, 11th 3rd insulating film, 11 ': 3rd insulating film spacer, 12, 14 photosensitive film Pattern, 13: nitride film, 15: third conductive layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2A 내지 도 2E에 본 발명에 의한 반도체장치 제조방법을 공정순서에 따라 도시하였다.2A to 2E illustrate a method of manufacturing a semiconductor device according to the present invention according to the process sequence.
먼저, 도 2A는 반도체기판(1)상에 제1절연막(2)과, 제1도전층(3), 제2절연막(4) 및 제2도전층(5)이 차례로 형성된 적층구조를 나타낸다. 이러한 적층구조는 예컨대, 플래쉬 메모리소자의 소거 및 프로그램에 사용되는 적층 게이트구조일 수 있으며, 이 경우, 상기 제1도전층(3)은 플로팅 게이트, 제2도전층(5)은 제어게이트일 수 있다. 또한, 상기 제1절연막(2)은 산화막, 질화막 또는 질화산화막일 수 있고, 제2절연막은 ONO(산화막/질화막/산화막)일 수 있다. 이와 같이 적층구조가 형성된 반도체기판(1) 전면에 제3절연막으로서, 예컨대, 산화막(11)을 형성한 후, 그위에 감광막을 도포하고 이를 선택적으로 노광 및 현상하여 소정의 제1감광막패턴(12)을 형성한다.First, FIG. 2A shows a lamination structure in which a first insulating film 2, a first conductive layer 3, a second insulating film 4, and a second conductive layer 5 are sequentially formed on a semiconductor substrate 1. The stacked structure may be, for example, a stacked gate structure used for erasing and programming a flash memory device. In this case, the first conductive layer 3 may be a floating gate and the second conductive layer 5 may be a control gate. have. In addition, the first insulating film 2 may be an oxide film, a nitride film, or a nitride oxide film, and the second insulating film may be ONO (oxide film / nitride film / oxide film). As such, after the oxide film 11 is formed on the entire surface of the semiconductor substrate 1 having the stacked structure, for example, an oxide film 11 is formed thereon, a photoresist film is applied thereon, and a predetermined first photoresist film pattern 12 is selectively exposed and developed. ).
이어서 도 2B에 도시한 바와 같이 상기 제1감광막패턴(12)을 마스크로 이용하여 상기 제3절연막(11))을 소정두께가 남도록 부분적으로 건식식각하여 상기 적층 구조의 일측면에 절연막스페이서(11')를 형성한다. 이어서 상기 제1감광막패턴을 제거한 후, 기판 전면에 질화막(13)을 형성하고, 그위에 다시 감광막을 도포하고 이를 선택적으로 노광 및 현상하여 소정의 제2감광막패턴(14)을 형성한다.Subsequently, as shown in FIG. 2B, the first insulating film pattern 12 is used as a mask to partially dry-etch the third insulating film 11 so that a predetermined thickness remains, and the insulating film spacer 11 is formed on one side of the laminated structure. Form '). Subsequently, after the first photoresist layer pattern is removed, the nitride film 13 is formed on the entire surface of the substrate, and the photoresist layer is further applied on the substrate, and the photoresist layer is selectively exposed and developed to form a predetermined second photoresist layer pattern 14.
다음에 도 2C와 같이 상기 제2감광막패턴14)을 마스크로 이용하여 상기 질화막(13)을 예컨대 SF6가스를 이용하여 건식식각하여 상기 적층구조의 일측면에 질화막 스페이서(13')을 형성한다. 상기 질화막의 건식식각시 상기 산화막(11)에 대한 식각선택비가 3:1 이상이 되도록 식각조건을 설정하여 식각을 행하는 것이 바람직하다. 이때, 질화막 스페이서(13')은 상기 절연막 스페이서(11')상에 형성되도록 하여 이중 절연막 스페이서를 형성한다.Next, as shown in FIG. 2C, the nitride film 13 is dry-etched using, for example, SF 6 gas, using the second photoresist film pattern 14 as a mask to form a nitride film spacer 13 ′ on one side of the stack structure. . In the dry etching of the nitride film, etching is preferably performed by setting etching conditions such that an etching selectivity with respect to the oxide film 11 is 3: 1 or more. In this case, the nitride film spacer 13 ′ is formed on the insulating film spacer 11 ′ to form a double insulating film spacer.
이어서 상기 제2감광막패턴(14)을 제거한 후, 도 2D와 같이 습식식각을 행하여 상기 노출된 제3절연막(11)을 제거한다. 이때, 도 2D의 (B)에 나타낸 바와 같이 상기 습식식각시 질화막 스페이서(13') 하부의 제3절연막 부위는 식각되었지만 상기 절연막 스페이서(11)는 제거되지 않는다.Subsequently, after the second photoresist layer pattern 14 is removed, the exposed third insulating layer 11 is removed by wet etching as shown in FIG. 2D. In this case, as shown in FIG. 2D (B), the portion of the third insulating layer under the nitride nitride spacer 13 ′ during the wet etching is etched, but the insulating layer spacer 11 is not removed.
다음에 도 2E와 같이 기판 전면에 제3도전층(15)을 형성하게 되면, 상기 제1도전층(2)과 제3도전층(15)이 상기 절연막 스페이서(11')에 의해 분리됨으로써(B')로 나타낸 바와 같이 브릿지를 완전히 방지할 수 있게 된다. 상기 제3도전층은 플래쉬 메모리의 선택게이트일 수 있다.Next, as shown in FIG. 2E, when the third conductive layer 15 is formed on the entire surface of the substrate, the first conductive layer 2 and the third conductive layer 15 are separated by the insulating film spacer 11 ′ ( As indicated by B '), the bridge can be completely prevented. The third conductive layer may be a selection gate of the flash memory.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 반도체소자에 치명적인 영향을 주는 도전층간 브릿지를 간단한 식각공정을 통해 형성되는 이중 절연막 스페이서에 의해 방지함으로써 반도체소자 제조시의 수율 및 신뢰성을 향상시키고 소자의 불량율을 감소시킬 수 있게 된다.According to the present invention, it is possible to prevent the inter-conductor bridges, which have a fatal effect on the semiconductor devices, by the double insulating film spacers formed through a simple etching process, thereby improving the yield and reliability in manufacturing the semiconductor devices and reducing the defective rate of the devices. .
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076411A KR19980057141A (en) | 1996-12-30 | 1996-12-30 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076411A KR19980057141A (en) | 1996-12-30 | 1996-12-30 | Semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980057141A true KR19980057141A (en) | 1998-09-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960076411A KR19980057141A (en) | 1996-12-30 | 1996-12-30 | Semiconductor device manufacturing method |
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| Country | Link |
|---|---|
| KR (1) | KR19980057141A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100815968B1 (en) * | 2007-05-17 | 2008-03-24 | 주식회사 동부하이텍 | Method for manufacturing of semiconductor device |
-
1996
- 1996-12-30 KR KR1019960076411A patent/KR19980057141A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100815968B1 (en) * | 2007-05-17 | 2008-03-24 | 주식회사 동부하이텍 | Method for manufacturing of semiconductor device |
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