KR950002036A - Method for manufacturing charge storage electrode with increased surface area - Google Patents

Method for manufacturing charge storage electrode with increased surface area Download PDF

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Publication number
KR950002036A
KR950002036A KR1019930010937A KR930010937A KR950002036A KR 950002036 A KR950002036 A KR 950002036A KR 1019930010937 A KR1019930010937 A KR 1019930010937A KR 930010937 A KR930010937 A KR 930010937A KR 950002036 A KR950002036 A KR 950002036A
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KR
South Korea
Prior art keywords
conductive layer
photoresist
layer
storage electrode
charge storage
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Application number
KR1019930010937A
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Korean (ko)
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KR970004323B1 (en
Inventor
우상호
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR93010937A priority Critical patent/KR970004323B1/en
Publication of KR950002036A publication Critical patent/KR950002036A/en
Application granted granted Critical
Publication of KR970004323B1 publication Critical patent/KR970004323B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 표면적이 증대된 전하저장전극 제조 방법에 관한 것으로, 반도체 소자의 고집적화에 따라 제한된 셀 면적내에서 충분한 양의 전하량을 확보하기 위하여 2개의 핀형 전하저장전극과 함께 형성된 스페이서 터널을 사이에 두고 반원형의 곡면 전하저장전극이 추가형성되도록 하여 전하저장전극의 단차를 높이지 않고도 충분한 전하량을 얻을수 있는 표면적이 증대된 전하저장전극 제조 방법에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a charge storage electrode having an increased surface area, and having a spacer tunnel formed with two fin-type charge storage electrodes in order to secure a sufficient amount of charge within a limited cell area due to high integration of semiconductor devices. A method of manufacturing a charge storage electrode having an increased surface area in which a semicircular curved charge storage electrode is additionally formed to obtain a sufficient charge amount without raising the step difference of the charge storage electrode is described.

Description

표면적이 증대된 전하저장전극 제조방법Method for manufacturing charge storage electrode with increased surface area

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1D도는 본 발명에 따라 전하저장전극을 형성하는 단계를 나타내는 단면도, 제 2 도는 제1A 내지 제1D도에 적용되는 마스크 배치도.1A to 1D are cross-sectional views illustrating the step of forming a charge storage electrode according to the present invention, and FIG. 2 is a mask arrangement diagram applied to FIGS. 1A to 1D.

Claims (2)

반도체소자의 전하저장전극 제조방법에 있어서, ＭＯＳ트랜지스터가 형성된 제 2절연막(12) 상부에 제1도전층(13), 제1산화막(14), 제2도전층(15) 및 제2산화막(16)을 순차적으로 형성한 후, 예정된 위치에 콘택홀(17)을 형성한 다음, 상기 콘택홀(17)을 포함한 제 2산화막(16)상에 제3도전층(18)을 형성하는 단계와, 상기 제3도전층(18) 상부에 제1포토레지스트(40)를 도포하여 제1마스크(19)를 사용해서 상기 제1포토레지스트(40)를 패턴화한 후, 상기 패턴화된 제1포토레지스트(40)를 식각 마스크로 하여 비등방성 식각 공정으로 상기 제3도전층(18), 제2산화막(16), 제2도전층(15) 및 제1산화막(14)을 순차적으로 식각한 다음, 상기 제1포토레지스트(40)를 제거하고, 전체구조상부에 CVD산화막(20)을 형성하는 단계와, 상기 CVD산화막(20)을 스페이서 식각공정으로 식각하여 제5 및 제6스페이서(26 및 27)를 형성한 후, 제 4도전층(21)을 형성한 다음, 상기 제4도전층(21)상부에 제2포토레지스트(41)를 도포하여 제2마스크(22)를 사용해서 상기 제2포토레지스트(41)를 패턴화한 후, 상기 패턴화된 제2포토레지스트(41)를 식각마스크로 하여 비등방석 식각공정으로 제4도전층(21), 제3도전층(18), 제2산화막(16), 제2도전층(15), 제1산화막(14), 제5 및 제6스페이서(26 및 27)을 식각하는 단계와, 상기 단계로부터 습식식각 용액에 담그어 개방된 부분을 통해 각 도전층(21,18,15 및 13) 사이에 존재하는 상기 제1 및 제2산화막(14 및 16), 제1 및 제2스페이서(26 및 27)를 식각한 후, 상기 제1도전층(13)을 식각한 다음, 제2포토레지스트(41)를 제거하는 단계로 이루어지는 것을 특징으로 하는 표면적이 증대된 전하저장전극 제조방법.In the method of manufacturing a charge storage electrode of a semiconductor device, the first conductive layer 13, the first oxide layer 14, the second conductive layer 15, and the second oxide layer (above the second insulating layer 12 on which the MOSFET is formed) Forming the contact holes 17 at predetermined positions, and then forming the third conductive layer 18 on the second oxide film 16 including the contact holes 17. After coating the first photoresist 40 on the third conductive layer 18 to pattern the first photoresist 40 using the first mask 19, the patterned first The third conductive layer 18, the second oxide layer 16, the second conductive layer 15, and the first oxide layer 14 were sequentially etched by an anisotropic etching process using the photoresist 40 as an etching mask. Next, the first photoresist 40 is removed, the CVD oxide film 20 is formed on the entire structure, and the CVD oxide film 20 is etched by a spacer etching process. After forming the sixth spacers 26 and 27, the fourth conductive layer 21 is formed, and then a second photoresist 41 is applied on the fourth conductive layer 21 to form a second mask 22. After the second photoresist 41 is patterned using the C-type photoresist, the fourth conductive layer 21 and the third conductive layer are subjected to an anisotropic etching process using the patterned second photoresist 41 as an etching mask. Etching the layer 18, the second oxide film 16, the second conductive layer 15, the first oxide film 14, the fifth and sixth spacers 26 and 27, and the wet etching solution from the step. The first and second oxide films 14 and 16 and the first and second spacers 26 and 27 existing between the conductive layers 21, 18, 15, and 13 are etched through the opened portions. After that, the first conductive layer 13 is etched and then the second photoresist 41 is removed. 제 1 항에 있어서, 상기 제1,2,3 및 4도전층(13,15,18 및 21) 각각은 인－시투 포스포러스 폴리 실리콘 박막을 이용하여 형성되는 것을 특징으로 하는 표면적이 증대된 전하저장전극 제조방법.The surface-enhanced charge of claim 1, wherein each of the first, second, third and fourth conductive layers 13, 15, 18, and 21 is formed using an in-situ phosphorus polysilicon thin film. Storage electrode manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93010937A 1993-06-16 1993-06-16 Electrode storage manufacturing method for surface area increasing KR970004323B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93010937A KR970004323B1 (en) 1993-06-16 1993-06-16 Electrode storage manufacturing method for surface area increasing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93010937A KR970004323B1 (en) 1993-06-16 1993-06-16 Electrode storage manufacturing method for surface area increasing

Publications (2)

Publication Number Publication Date
KR950002036A true KR950002036A (en) 1995-01-04
KR970004323B1 KR970004323B1 (en) 1997-03-26

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KR93010937A KR970004323B1 (en) 1993-06-16 1993-06-16 Electrode storage manufacturing method for surface area increasing

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KR970004323B1 (en) 1997-03-26

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