KR930018732A - Manufacturing Method of Semiconductor Memory Device - Google Patents

Manufacturing Method of Semiconductor Memory Device Download PDF

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Publication number
KR930018732A
KR930018732A KR1019920002814A KR920002814A KR930018732A KR 930018732 A KR930018732 A KR 930018732A KR 1019920002814 A KR1019920002814 A KR 1019920002814A KR 920002814 A KR920002814 A KR 920002814A KR 930018732 A KR930018732 A KR 930018732A
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South Korea
Prior art keywords
forming
capacitor
storage electrode
photoresist
contact hole
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KR1019920002814A
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Korean (ko)
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KR960004466B1 (en
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신지철
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김광호
삼성전자 주식회사
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Publication of KR930018732A publication Critical patent/KR930018732A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 메모리장치의 커패시터 제조방법에 관한 것으로, 소오스영역, 드레인영역 및 게이트전극으로 구성되는 하나의 트랜지스터와, 스토리지전극, 유전체막 및 플레이트전극으로 구성되는 하나의 커패시터로 이루어진 메모리셀들이 규칙적으로 반도체기판에 형성된 반도체기판에 형성된 반도체 메모리장치의제조방법에 있어서, 상기 커패시터의 스토리지전극 형성을 위한 공정은, 상기 소오스영역에 형성된 콘택홀내에 절연물질로 이루어진 원통의 기둥을 형성하는 공정과, 결과물 전면에 제1도전층을 형성하는 공정, 및 각 커패시터 단위로 상기 제1도전층을 한정함으로써 상기 스토리지전극을 완성하는 공정을 구비하는 것을 특징으로 하는 본 발명에 의하면 큰 패커시터용량을 갖는 원통형 구조의 커패시터를 간단한 공정으로 제조할 수있으며 콘택홀 크기 및 커패시터용량을 저온플라즈마 산화막의 두께 및 포토레지스트 마스크두께를 조절함으로써 쉽게 제어할 수 있어 원가절감, 제조공정일 단축 및 제조에 드는 시간과 노력의 감소가 가능하게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, wherein memory cells composed of one transistor composed of a source region, a drain region, and a gate electrode, and one capacitor composed of a storage electrode, a dielectric layer, and a plate electrode are regularly In the method of manufacturing a semiconductor memory device formed on a semiconductor substrate formed on a semiconductor substrate, the process for forming a storage electrode of the capacitor, the process of forming a cylindrical pillar made of an insulating material in the contact hole formed in the source region; According to the present invention, there is provided a process for forming a first conductive layer on the entire surface of the resultant, and the step of completing the storage electrode by limiting the first conductive layer to each capacitor unit. Capacitors of Structure And it is possible that the contact hole size and the capacity of the capacitor by controlling the thickness of the photoresist mask and the thickness of the low temperature plasma oxide film is easy to control it cost reduction, manufacturing process shortening and work reduction of the time and effort to manufacture.

Description

반도체 메모리장치의 제조방법Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3a도 내지 제3e도는 본 발명의 일실시예에 의한 반도체 메모리장치의 커패시터 제조방법을 도시한 단면도.3A to 3E are cross-sectional views illustrating a capacitor manufacturing method of a semiconductor memory device according to an embodiment of the present invention.

제4도는 본 발명에 의한 반도체 메모리장치의 커패시터의 스토리지 전극을 나타낸 사시도.4 is a perspective view showing a storage electrode of a capacitor of a semiconductor memory device according to the present invention.

Claims (9)

소오스영역, 드레인영역 및 게이트전극으로 구성되는 하나의 트랜지스터와, 스토리지전극, 유전체막 및 플레이트전극으로 구성되는 하나의 커패시터로 이루어진 메모리셀들이 규칙적으로 반도체기판에 형성된 반도체 메모리장치의 제조방법에 있어서, 상기 커패시터의 스토리지전극 형성을 위한 공정은, 상기 소오스영역에 형성된 콘택홀내에 절연물질로 이루어진 원통의 기둥을 형성하는 공정과, 결과물 전면에 제1도전층을 형성하는 공정, 및 각 커패시터 단위로 상기 제1도전층을 한정함으로써 상기 스토리지전극을 완성하는 공정을 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.A method of manufacturing a semiconductor memory device in which memory cells each including a transistor consisting of a source region, a drain region, and a gate electrode, and a capacitor consisting of a storage electrode, a dielectric film, and a plate electrode are regularly formed on a semiconductor substrate, The process for forming a storage electrode of the capacitor may include forming a cylindrical pillar made of an insulating material in a contact hole formed in the source region, forming a first conductive layer on the entire surface of the resultant, and for each capacitor unit. And a step of completing the storage electrode by defining a first conductive layer. 제1항에 있어서, 상기 절연물질로 이루어진 원통의 기둥을 형성하는 공정은, 상기 트랜지스터가 형성되어 있는 반도체기판 전면에 층간절연층을 형성하는 공정, 결과물 전면에 포토레지스트를 도포한 후, 포토리소그래피 공정에 의해 상기 소오스영역상에 원기둥 형태의 콘택홀 패턴을 형성하는 공정, 결과물전면에 절연물질을 증착하여 절연막을 형성한 후 이방성식각하여 상기 포토레지스트로 이루어진 콘택홀 패턴의 측벽에만 상기 절연막을 남김과 더불어 노출된 상기 충간절연층을 제거하여 반도체기판을 노출시키는 공정, 및 상기 포토레지스트 패턴을 제거하는 공정으로 구성된 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 1, wherein the forming of the cylindrical pillar made of the insulating material comprises forming an interlayer insulating layer on the entire surface of the semiconductor substrate on which the transistor is formed, applying photoresist on the entire surface of the resultant, and then performing photolithography. Forming a cylindrical contact hole pattern on the source region by a process; depositing an insulating material on the entire surface of the resultant to form an insulating film, and then anisotropically etching and leaving the insulating film only on sidewalls of the contact hole pattern made of the photoresist; And removing the exposed interlayer insulating layer to expose a semiconductor substrate, and removing the photoresist pattern. 제2항에 있어서, 상기 충간절연층은 HTO층임을 특징으로 하는 반도체메모리장치의 제조방법.The method of claim 2, wherein the interlayer insulating layer is an HTO layer. 제2항에 있어서, 상기 포토레지스트는 1㎛~1.5㎛의 두께로 도포하는 것을 특징으로 하는 반도체메모리장치의 제조방법.The method of claim 2, wherein the photoresist is applied in a thickness of 1 μm to 1.5 μm. 제2항에 있어서, 상기 절연막은 180℃~230℃의 온도에서 플라즈마 방식에 의해 증착된 산화막임을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 2, wherein the insulating film is an oxide film deposited by a plasma method at a temperature of 180 ° C. to 230 ° C. 4. 제5항에 있어서, 상기 산화막의 두께는 900Å~1200Å임을 특징으로 하는 반도체메모리장치의 제조방법.6. The method of claim 5, wherein the oxide film has a thickness of 900 mW to 1200 mW. 제2항에 있어서, 상기 이방성식각은 반응가스의 유량 O215SCCM, CHF3133 SCCM, 52m Torr, 590V의 조건에서 8분간 행하는 건식식각임을 특징으로 하는 반도체메모리장치의 제조방법.The method of claim 2, wherein the anisotropic etching is a dry etching performed for 8 minutes under conditions of a reaction gas flow rate of O 2 15 SCCM, CHF 3 133 SCCM, 52 m Torr, and 590 V. 4. 제2항에 있어서, 상기 포토레지스트를 제거하는 공정은 O2플라즈마를 이용한 건식식각과 H2SO4를 이용한 습식식각에 의해 행하는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 2, wherein the removing of the photoresist is performed by dry etching using an O 2 plasma and wet etching using H 2 SO 4 . 제1항에 있어서, 상기 제1도전층은 불순물이 도우프된 다결정 실리콘을 2300Å~2700Å 두께로 증착하여 형성함을 특징으로 하는 반도체메모리장치의 제조방법.2. The method of claim 1, wherein the first conductive layer is formed by depositing polycrystalline silicon doped with impurities to a thickness of 2300 GPa to 2700 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920002814A 1992-02-24 1992-02-24 Semiconductor memory device fabrication process KR960004466B1 (en)

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KR930018732A true KR930018732A (en) 1993-09-22
KR960004466B1 KR960004466B1 (en) 1996-04-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100599440B1 (en) * 2000-06-30 2006-07-12 주식회사 하이닉스반도체 Method for manufacture capicitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100599440B1 (en) * 2000-06-30 2006-07-12 주식회사 하이닉스반도체 Method for manufacture capicitor

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